IEICE TRANSACTIONS on Electronics
1.9 GHz Si Direct Conversion Receiver IC for QPSK Modulation Systems
Summary :
A 1.9GHz direct conversion receiver(DCR) chip which integrates an LNA, I/Q mixers(MIX), active lowpass filters(LDF) and variable gain amplifiers(VGA) was fabricated. Because the DCR for QPSK modulation systems is sensitive to the 2nd-order nonlinearity, linearization techniques are adopted in MIX and LPF. The DCR chip was fabricated using a BiCMOS process, and the die size is 5.1 mm by 5.1mm. The chip can operate from 2.7 V supply voltage and consumes 165mW when all the functions are activated. Suppression of local signal radiation and the 2nd-order distortion indicate the feasibility of Si-based DCR for QPSK modulation systems such as PHS.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.5 pp.644-649
- Publication Date
- 1996/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Microwave Devices for Mobile Communications)
- Category
- Active Devices
Authors
Chikau TAKAHASHI
Ryuichi FUJIMOTO
Satoshi ARAI
Tetsuro ITAKURA
Takashi UENO
Hiroshi TSURUMI
Hiroshi TANIMOTO
Shuji WATANABE
Kenji HIRAKAWA
Keyword
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Chikau TAKAHASHI, Ryuichi FUJIMOTO, Satoshi ARAI, Tetsuro ITAKURA, Takashi UENO, Hiroshi TSURUMI, Hiroshi TANIMOTO, Shuji WATANABE, Kenji HIRAKAWA, "1.9 GHz Si Direct Conversion Receiver IC for QPSK Modulation Systems" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 5, pp. 644-649, May 1996, doi: .
Abstract: A 1.9GHz direct conversion receiver(DCR) chip which integrates an LNA, I/Q mixers(MIX), active lowpass filters(LDF) and variable gain amplifiers(VGA) was fabricated. Because the DCR for QPSK modulation systems is sensitive to the 2nd-order nonlinearity, linearization techniques are adopted in MIX and LPF. The DCR chip was fabricated using a BiCMOS process, and the die size is 5.1 mm by 5.1mm. The chip can operate from 2.7 V supply voltage and consumes 165mW when all the functions are activated. Suppression of local signal radiation and the 2nd-order distortion indicate the feasibility of Si-based DCR for QPSK modulation systems such as PHS.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_5_644/_p
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@ARTICLE{e79-c_5_644,
author={Chikau TAKAHASHI, Ryuichi FUJIMOTO, Satoshi ARAI, Tetsuro ITAKURA, Takashi UENO, Hiroshi TSURUMI, Hiroshi TANIMOTO, Shuji WATANABE, Kenji HIRAKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={1.9 GHz Si Direct Conversion Receiver IC for QPSK Modulation Systems},
year={1996},
volume={E79-C},
number={5},
pages={644-649},
abstract={A 1.9GHz direct conversion receiver(DCR) chip which integrates an LNA, I/Q mixers(MIX), active lowpass filters(LDF) and variable gain amplifiers(VGA) was fabricated. Because the DCR for QPSK modulation systems is sensitive to the 2nd-order nonlinearity, linearization techniques are adopted in MIX and LPF. The DCR chip was fabricated using a BiCMOS process, and the die size is 5.1 mm by 5.1mm. The chip can operate from 2.7 V supply voltage and consumes 165mW when all the functions are activated. Suppression of local signal radiation and the 2nd-order distortion indicate the feasibility of Si-based DCR for QPSK modulation systems such as PHS.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - 1.9 GHz Si Direct Conversion Receiver IC for QPSK Modulation Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 644
EP - 649
AU - Chikau TAKAHASHI
AU - Ryuichi FUJIMOTO
AU - Satoshi ARAI
AU - Tetsuro ITAKURA
AU - Takashi UENO
AU - Hiroshi TSURUMI
AU - Hiroshi TANIMOTO
AU - Shuji WATANABE
AU - Kenji HIRAKAWA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1996
AB - A 1.9GHz direct conversion receiver(DCR) chip which integrates an LNA, I/Q mixers(MIX), active lowpass filters(LDF) and variable gain amplifiers(VGA) was fabricated. Because the DCR for QPSK modulation systems is sensitive to the 2nd-order nonlinearity, linearization techniques are adopted in MIX and LPF. The DCR chip was fabricated using a BiCMOS process, and the die size is 5.1 mm by 5.1mm. The chip can operate from 2.7 V supply voltage and consumes 165mW when all the functions are activated. Suppression of local signal radiation and the 2nd-order distortion indicate the feasibility of Si-based DCR for QPSK modulation systems such as PHS.
ER -
English
