A fast fc automatic tuning circuit suitable for WCDMA systems is proposed. The circuit employs master-slave architecture using digitally controlled Gm-C filter for avoiding long transient response. The tuning feedback loop contains a 2-bit up-down counter ADC for fast tuning operation. Furthermore, to avoid degradation of fc tuning accuracy due to reference feedthrough, an analog loop filter with notch located near reference frequency is used. The fast fc automatic tuning circuit is fabricated in a SiGe BiCMOS process. The tuning time within 200 µs is achieved for 35 chips from 2 lots and the standard deviation of 25.5 kHz is obtained for the average fc of 2.12 MHz.

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.

From the viewpoint of a low-power pipeline ADC design, a comparison between two conventional power reduction techniques is discussed. The comparison shows that the amplifier sharing technique has an advantage in terms of the power reduction effect. To confirm the advantage, a test chip of 10-bit 80-MSPS ADC using the amplifier sharing technique is fabricated. The test chip dissipates 55 mW at 80 MSPS (Mega Sample Per Second).

This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.

An operational amplifier is one of the key functional blocks and is widely used in analog and mixed-signal circuits. For low-power consumption, many techniques such as class AB and slew-rate enhancement have been proposed. Although phase compensation is related to power consumption, it has not been clearly discussed from the viewpoint of the power consumption. In this paper, the conventional and the improved Miller compensations and the phase compensation by introducing a new zero are dicussed for low-power operational amplifiers.

A novel automatic quality factor (Q) tuning scheme for an low-power and wideband active-RC filter is presented. Although Q-tuning is effective to reduce the power consumption of wideband active-RC filters, there are several problems since the Q-tuning normally relies on a magnitude locked loop (MLL). MLL is not accurate due to the amplitude detection circuits, and occupied area and power consumption tends to be large due to its complexity. In addition, flexibility to the reference signal may be the problem, since the reference signal which has a fixed accurate frequency is required. In order to solve these problems, we propose a Q-tuning scheme, which does not require a MLL. Therefore, proposed Q-tuning scheme has good accuracy, small die area, low power consumption and flexibility to the reference signal. In our proposed scheme, Q is tuned by adjusting the phase of an integrator to 90 degrees. The phase of an integrator is adjusted by detecting and controlling the oscillation frequency of a two-stage ring-integrator to the cutoff frequency of a filter, since the phase shift of an integrator is exactly 90 degrees at the oscillation frequency. The frequency is easily detected and controlled by counters and variable resistors, respectively. The Q-tuning circuit with a 5th-order Chebyshev LPF is implemented in a 0.13 µm CMOS technology. The tuning circuit occupies 0.12 mm2 and consumes 2.6 mW from 1.2 V supply.

A fully balanced (FB) transconductor using two multi-input single-ended (SE) CMOS transconductors is proposed, where the transconductors use MOS transitors operating in a triode region for achieving a wide linear input-range. SE circuits are easier to design than differential circuits and inherently reject common-mode (CM) signals. The multi-input structure is used to make a CM feedback loop and to determine an output CM voltage. A high-output-resistance current mirror is used in converting a differential signal to a single-ended signal in order to achieve a high common-mode rejection ratio (CMRR) and a high output-resistance of the transconductor. The FB transconductor achieves a 2-Vpp linear input range at a 2.5-V power supply and consumes 1.74 mA. The output resistance of the FB transconductor is 2 MΩ. It operates at 2 V with a linear input-range of 1.2 Vpp and at 1.6 V with a linear input-range of 0.9 Vpp. A 2.5-V 2.5-MHz FB Gm-C filter using the FB transconductors achieved a CMRR of 45 dB and a passband IIP3 of 32 dBm.

A simple phase compensation technique with improved power supply rejection ratio (PSRR) for CMOS opamps is proposed. This technique is based on feeding back a current proportional to a derivative of the voltage difference between an output and an input, and does not require a common-gate circuit or a noise-free bias for the circuit. The proposed technique requires only two additional transistors, which are connected to the differential pair of transistors in a cascade manner, and the compensation capacitor is connected to the source node of the additional transistor. Experimental results show an improvement of more than 20 dB in the PSRR at high frequencies, comparing the technique with a Miller compensation. This technique also improves the unity gain frequency and the phase margin from 0.9 MHz and 17 to 1.8 MHz and 44 for 200 pF load capacitance, respectively.

This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14,mm2 and the ADC consumes 36 mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an figure of Merit (FoM) of 300 fJ/conv. is achieved.

A simple modeling technique for symmetric inductors is proposed. Using the proposed technique, all model parameters for an equivalent circuit of symmetric inductors are easily calculated from geometric, process and substrate resistance parameters without using electromagnetic (EM) simulators. Comparison of simulated results with measured results verifies the effectiveness of the proposed modeling technique up to 5 GHz with center-tapped or non-center-tapped configurations.

In a direct conversion receiver for mobile communication, it is important to reduce power dissipation. Because a low pass filter in a direct conversion receiver must suppress adjacent channel signals, a high order and high power dissipation is often required in the low pass filter. We propose a new phase compensation technique suitable for a low power transconductor used in a GmC filter as a low pass filter. The new phase compensation technique reduces 10% of power dissipation.

This paper examines the design considerations for an opamp to be used in a low-power consumption LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The experimental results support our opamp design approach and indicate the feasibility of a 10 µA quiescent current opamp.

A fully differential direct conversion receiver IC for W-CDMA is presented. The receiver IC consists of an LNA, a quadrature demodulator, low-pass filters (LPFs), and variable gain amplifiers (VGAs). In order to suppress DC offset, which is the most important issue in a direct conversion system, an active harmonic mixer is applied to the quadrature demodulator. Furthermore, a receiving system, including the LNA and an RF filter, adopts a differential architecture to reduce local signal leakage, which generates DC offset. Performance of the entire receiving system was evaluated and DC offset in steady state was measured at only 40 mV. Moreover, DC offset variation at the LNA gain change, which has the largest affect on the receiving performance, was limited to 70 mV, which is less than -10 dB compared to desired signal strength. It was confirmed by computer simulation that the DC offset variation at the LNA gain change did not degrade bit error rate (BER) performance at all.

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.

This paper describes a low-power-supply 2-GHz CMOS up-converter. A current-mode mixing method using current adding and self-switching mixers is proposed for 1-V operation. The current-mode up-converter achieves conversion gain of 6.7 dB and linearity of 6.5-dBm OIP3 at 1 V. Balanced configuration and DC offset canceller reduce LO leakage below -40 dBc even with 20-mV Vth mismatches. The bias circuit of the IC is designed to maintain constant conversion gain for variation of temperature for practical usage. The measurement results indicate the proposed up-converter is applicable for future wireless systems.

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant gm, etc. ), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc. ) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

An LCD Driver IC includes more than 300 buffer amplifiers on a single chip. The phase compensation capacitors (on-chip Miller capacitors) for the amplifiers are more than 1000 pF and occupy a large chip area. This paper describes a two-gain-stage amplifier in which an on-chip Miller capacitor is not used for phase compensation in an LCD Driver IC. In the proposed amplifier, phase compensation is achieved only by a newly introduced zero, which is formed by the load capacitance and a phase compensation resistor connected between the output of the amplifier and the capacitive load. Designs of the phase compensation resistor and the amplifier before compensation are discussed, considering a typical load capacitance range. The test chip was fabricated. The newly introduced zero successfully stabilized the amplifier. The chip area for the amplifier was reduced by 30-40%, compared with our previously reported one. The current consumption of the amplifier was only 5 µA. The experimental results of the fabricated test chip support that the proposed amplifier is suitable to an LCD driver IC with a smaller chip area.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.