IEICE TRANSACTIONS on Fundamentals
A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS
Summary :
This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14,mm2 and the ADC consumes 36 mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an figure of Merit (FoM) of 300 fJ/conv. is achieved.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.7 pp.1552-1561
- Publication Date
- 2013/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.1552
- Type of Manuscript
- PAPER
- Category
- Analog Signal Processing
Authors
Masanori FURUTA
Toshiba Corporation
Ippei AKITA
Toyohashi University of Technology
Junya MATSUNO
Toshiba Corporation
Tetsuro ITAKURA
Toshiba Corporation
Keyword
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Masanori FURUTA, Ippei AKITA, Junya MATSUNO, Tetsuro ITAKURA, "A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 7, pp. 1552-1561, July 2013, doi: 10.1587/transfun.E96.A.1552.
Abstract: This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14,mm2 and the ADC consumes 36 mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an figure of Merit (FoM) of 300 fJ/conv. is achieved.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.1552/_p
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@ARTICLE{e96-a_7_1552,
author={Masanori FURUTA, Ippei AKITA, Junya MATSUNO, Tetsuro ITAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS},
year={2013},
volume={E96-A},
number={7},
pages={1552-1561},
abstract={This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14,mm2 and the ADC consumes 36 mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an figure of Merit (FoM) of 300 fJ/conv. is achieved.},
keywords={},
doi={10.1587/transfun.E96.A.1552},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1552
EP - 1561
AU - Masanori FURUTA
AU - Ippei AKITA
AU - Junya MATSUNO
AU - Tetsuro ITAKURA
PY - 2013
DO - 10.1587/transfun.E96.A.1552
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2013
AB - This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14,mm2 and the ADC consumes 36 mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an figure of Merit (FoM) of 300 fJ/conv. is achieved.
ER -
English
