We propose a sound field control system to control the sound over a wide area within a room by reducing the influence of the reproduction space using power envelope inverse filtering (PEIF). Envelopes of the impulse response within the room have approximately the same shape at all observation points. Therefore, the proposed sound field control system can control with a small number of loudspeakers a wider area by reducing reverberation in the room through envelope processing. We present experimental data demonstrating that the proposed PEIF system can provide better control than a system that uses minimum phase inverse filtering (MPIF), which is conventionally used for reducing reverberation. Improvement was observed across the frequency band, especially above 1 kHz. Additionally, our PEIF system is more effective over the high-frequency range.

We propose a computing method for linear convolution and linear correlation between sequences using discrete cosine transform (DCT). Zero-padding is considered as well as linear convolution using discrete Fourier transform (DFT). Analyzing the circular convolution between symmetrically extended sequences, we derive the condition for zero-padding before and after the sequences. The proposed method can calculate linear convolution for any filter and also calculate linear correlation without reversing one of the input sequences. The computational complexity of the proposed method is lower than that of linear convolution using DFT.

This work presents a four-channel headset achieving a 5.1-channel-like hearing experience using a low-complexity head-related transfer function (HRTF) model and a simplified reverberator. The proposed down-mixing architecture enhances the sound localization capability of a headset using the HRTF and by simulating multiple sound reflections in a room using Moorer's reverberator. Since the HRTF has large memory and computation requirements, the common-acoustical-pole and zero (CAPZ) model can be used to reshape the lower-order HRTF model. From a power consumption viewpoint, the CAPZ model reduces computation complexity by approximately 40%. The subjective listening tests in this study shows that the proposed four-channel headset performs much better than stereo headphones. On the other hand, the four-channel headset that can be implemented by off-the-shelf components preserves the privacy with low cost.

This paper describes a unified VLSI architecture which can be applied to various types of transforms used in MPEG-2/4, H.264, VC-1, AVS and the emerging new video coding standard named HEVC (High Efficiency Video Coding). A novel design named configurable butterfly array (CBA) is also proposed to support both the forward transform and the inverse transform in this unified architecture. Hadamard transform or 4/8-point DCT/IDCT are used in traditional video coding standards while 16/32-point DCT/IDCT are newly introduced in HEVC. The proposed architecture can support all these transform types in a unified architecture. Two levels (architecture level and block level) of hardware sharing are adopted in this design. In the architecture level, the forward transform can share the hardware resource with the inverse transform. In the block level, the hardware for smaller size transform can be recursively reused by larger size transform. The multiplications of 4 or 8-point transform are implemented with Multiplierless MCM (Multiple Constant Multiplication). In order to reduce the hardware overhead, the multiplications of 16/32 point DCT are implemented with ICM (input-muxed constant multipliers) instead of MCM or regular multipliers. The proposed design is 51% more area efficient than previous work. To the author's knowledge, this is the first published work to support both forward and inverse 4/8/16/32-point integer transform for HEVC standard in a unified architecture.

In this paper, we propose a step size control method capable of quickly canceling acoustic echo even when double talk continues from the echo path change. This method controls the step size by substituting the norm of the difference vector between the coefficient vectors of a main adaptive filter (Main-ADF) and a sub-adaptive filter (Sub-ADF) for the estimation error provided by the former. Actually, the number of taps of Sub-ADF is limited to a quarter of that of Main-ADF, and the larger step size than that applied to Main-ADF is given to Sub-ADF; accordingly the norm of the difference vector quickly approximates to the estimation error. The estimation speed can be improved by utilizing the norm of the difference vector for the step size control in Main-ADF. We show using speech signals that in single talk the proposed method can provide almost the same estimation speed as the method whose step size is fixed at the optimum one and verify that even in double talk the estimation error, quickly decreases.

This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14,mm² and the ADC consumes 36 mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an figure of Merit (FoM) of 300 fJ/conv. is achieved.

We propose a motor speed ripple elimination method using a state dependent disturbance observer (SDDOB). The SDDOB eliminates the state dependent disturbance in the system regardless of the operation frequency, input time delay and output time delay. The SDDOB and a main proportional integral (PI) controller constitute a robust motor speed controller. Experimental results show the effectiveness of the proposed method.

This paper presents a novel adaptable 4-moduli set {2^{n + k}, 2ⁿ+1, 2ⁿ-1, 2²ⁿ+1}. It offers diverse dynamic ranges (DRs) from 2⁵ⁿ-2ⁿ to 2^{5n + k}-2^{n + k} that are used to conquer the over-range issue in RNS-application hardware designs. The proposed adaptable set possesses the coarse parameter n and fine parameter k. It not only has better parallelism and larger dynamic range (DR) than the existing adaptive 3-moduli sets, but also holds more sizable and flexible than the general 4-moduli sets with single parameter. For the adaptable R-to-B conversion, this paper first derives a fast reverse converting algorithm based on Chinese Remainder Theorem (CRT) and then presents the efficient converter architecture. From the experimental results, the proposed adaptable converter achieves better hardware performance in various DRs. Based on TSMC 0.18 µm CMOS technology, the proposed converter design is implemented and its results get at least 20.93% saving of Area-Delay-Power (ADP) products on average when comparing with the latest converter works.

This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-centered 6T SRAM cells.

Binary sequences with good autocorrelation and large linear complexity have found many applications in communication systems. A construction of almost difference sets was given by Cai and Ding in 2009. Many classes of binary sequences with three-level autocorrelation could be obtained by this construction and the linear complexity of two classes of binary sequences from the construction have been determined by Wang in 2010. Inspired by the analysis of Wang, we deternime the linear complexity and the minimal polynomials of another class of binary sequences, i.e., the class based on the WG difference set, from the construction by Cai and Ding. Furthermore, a generalized version of the construction by Cai and Ding is also presented.

A unified construction for transforming binary sequences of balance or unbalance into quaternary sequences is presented. On the one hand, when optimal and balanced binary sequences with even period are employed, our construction is exactly the same Jang, et al.'s and Chung, et al.'s ones, which result in balanced quaternary sequences with optimal autocorrelation magnitude. On the other hand, when ideal and balanced binary sequences with odd period N are made use of, our construction produces new balanced quaternary sequences with optimal autocorrelation value (OAV), in which there are N distinct sequences in terms of cyclic shift equivalence, and includes Tang, et al.'s and Jang, et al.'s ones as special cases. In addition, when binary sequences without period 2ⁿ-1 or balance are employed, the transformation of Jang, et al.'s method is invalid, however, the proposed construction works very good. As a consequence, this unified construction allows us to construct optimal and balanced quaternary sequences from ideal/optimal balanced binary sequences with arbitrary period.

NAND multi-level cell (MLC) flash memories are widely used due to low cost and high capacity. However, the increased number of levels in MLC results in larger interference and errors. The errors in MLC flash memories tend to be directional and limited-magnitude. Many related works focus on asymmetric errors, but bidirectional errors also occur because of the bidirectional interference and the adjustment of the hard-decision reference voltages. To take advantage of the characteristics, we propose t bidirectional (l_u,l_d) limited-magnitude error correction codes, which can reduce errors more effectively. The proposed code is systematic, and can correct t bidirectional errors with upward and downward magnitude of l_u and l_d, respectively. The proposed method is advantageous in that the parity size is reduced, and it has lower bit error rate than conventional error correction codes with the same code rate.

This paper describes the breathing phantom built to test a six-degree-of freedom sensing device designed for use in Respiratory-Gated Radiotherapy (RGRT). It is focussed on the construction of a test bed that was designed to address tumour motion issues while, at the same time, behaving in much the same way as the human tissues when irradiated. The phantom can produce respiratory movement in three dimensions. Shift differences between the motion axes can be introduced. The position error in the worst case scenario is not greater that 0.4 mm. Emphasis is made on the technical limitations of current sensing technologies, especially with regard to acceleration sensitivity. This study demonstrates that the sensitivity of accelerometers used to sense tumour motion should be 0.05 mG or less.

Large-scale introduction of renewable energy such as photovoltaic energy and wind is a big motivation for renovating conventional grid systems. To be independent from existing power grids and to use renewable energy as much as possible, a decentralized energy network is proposed as a new grid system. The decentralized energy network is placed among houses to connect them with each other, and each house has a PV panel and a battery. A contribution of this paper is a network topology and battery size exploration for the decentralized energy network in order to make effective use of renewable energy. The proposed method for exploring the decentralized energy network design is inspired by the design methodology of VLSI systems, especially design space exploration in system-level design. The proposed method is based on mixed integer programming (MIP) base power flow optimization, and it was evaluated for all design instances. Experimental results show that the decentralized energy network has the following features. 1) The energy loss and energy purchased due to power shortage were not affected by each battery size but largely affected by the sum of all battery sizes in the network, and 2) the network topology did not largely affect the energy loss and the purchased energy. These results will become a useful guide to designing an optimal decentralized energy network for each region.

This study investigated the relationship between human use of automation and their sensitivity to changes in automation and manual performance. In the real world, automation and manual performance change dynamically with changes in the environment. However, a few studies investigated whether changes in automation or manual performance have more effect on whether users choose to use automation. We used two types of experimental tracking tasks in which the participants had to select whether to use automation or conduct manual operation while monitoring the variable performance of automation and manual operation. As a result, we found that there is a mutual relationship between human use of automation and their sensitivity to automation and manual performance changes. Also, users do not react equally to both automation and manual performance changes although they use automation adequately.

We investigate the utilization of vector registers (VRs) on reducing memory references for single instruction multiple data fast Fourier transform calculation. We propose to group the butterfly computations in several consecutive stages to maximize utilization of the available VRs and take the advantage of the symmetries in twiddle factors. All the butterflies sharing identical twiddle factors are clustered and computed together to further improve performance. The relationship between the number of fused stages and the number of available VRs is then examined. Experimental results on different platforms show that the proposed method is effective.

I. O'Connor et al. have proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) to generate some logic functions by using the double-gate (DG) carbon nanotube (CNT) FETs which have the ambipolar property [1]. This DRDLC consists of seven transistors to generate 14 logic functions which do not include the XOR and XNOR functions. On the other hand, K. Jabeur et al. have proposed a DRDLC to generate the whole set of 16 logic functions including XOR and XNOR by adding 4 or 8 transistors to O'Connor's circuit [5]. In this letter, we propose a DRDLC, which consists of only seven transistors, to generate the whole set of 16 logic functions by using DG-CNTFETs. Finally, we show that the number of transistors can be reduced compared to the conventional DRDLC to generate 16 logic functions.

The wide application of FMEA in reliability engineering is generally appreciated, and how to identify the failure modes is the key to it. Failure modes, however, rely only on specific components rather than the system architecture, and therefore could be reused in different FMEAs. A novel ontology-based method, to recognize and reuse specific failure modes in existing databases, is provided here, and a light weight tool is developed for this method. The method and the tool can also be used in other fields with similar scenarios.

Traditional imperfect fault coverage models only consider the coverage (including identification and isolation) of faulty components, and they do not consider the coverage of irrelevant (operational) components. One potential reason for the omission is that in these models the system is generally assumed to be coherent in which each component is initially relevant. In this paper, we first point out that an initially relevant component could become irrelevant afterwards due to the failures of some other components, and thus it is important to consider the handling of irrelevancy even the system is originally coherent. We propose an irrelevancy coverage model (IRCM) in which the coverage is extended to the irrelevant components in addition to the faulty components. The IRCM can not only significantly enhance system reliability by preventing the future system failures resulting from the not-covered failures of the irrelevant components, but may also play an important role in efficient energy use in practice by timely turning off the irrelevant components.

In this letter, a property of the characteristic matrix of the Rotation Symmetric Boolean Functions (RSBFs) is characterized, and a sufficient and necessary condition for RSBFs being 1st correlation-immune (1-CI for simplicity) is obtained. This property is applied to construct resilient RSBFs of order 1 (1-resilient for simplicity) on pq variables, where p and q are both prime consistently in this letter. The results show that construction and counting of 1-resilient RSBFs on pq variables are equivalent to solving an equation system and counting the solutions. At last, the counting of all 1-resilient RSBFs on pq variables is also proposed.

This paper introduces the concept of order complexity, which represents the minimum number of partial ordering operations to make a string of perfectly ordered symbols. A novel variable-length code expressing such order complexity using binary digits is proposed herein. The proposed code is general, uniquely decipherable, and useful for coding a string of random permuted symbols having unknown statistics or which are preferred to have a uniform distribution.

Gopalan, Klivans, and Zuckerman proposed a list-decoding algorithm for Reed-Muller codes. Their algorithm works up to a given list-decoding radius. Dumer, Kabatiansky, and Tavernier improved the complexity of the algorithm for binary Reed-Muller codes by using the well-known Plotkin construction. In this study, we propose a list-decoding algorithm for non-binary Reed-Muller codes as a generalization of Dumer et al.'s algorithm. Our algorithm is based on a generalized Plotkin construction, and is more suitable for parallel computation than the algorithm of Gopalan et al. Since the list-decoding algorithms of Gopalan et al., Dumer et al., and ours can be applied to more general codes than Reed-Muller codes, we give a condition for codes under which these list-decoding algorithms works.

The sub-channel is empty except each user's allocated sub-channel in an orthogonal frequency division multiple access (OFDMA) system. The scheme of cooperative communication using this empty sub-channel has been studied. But, because each user wastes the time slots in the cooperation phase, it is difficult to achieve the full rate. In this letter, a new cooperative communication scheme based on OFDMA is proposed to improve transmission rate in Rayleigh fading channel.

This letter investigates price-based power control for cognitive radio networks (CRNs) with interference cancellation. The base station (BS) of the primary users (PUs) will admit secondary users (SUs) to access by pricing their interference power under the interference power constraint (IPC). We give the optimal price for BS to maximize its revenue and the optimal interference cancellation order to minimize the total transmit power of SUs. Simulation results show the effectiveness of the proposed pricing scheme.

Square root-raised-cosine (SRRC) filters are used in many systems for spectrum shaping, which leads to a high peak-to-average power ratio (PAPR). Nevertheless, some applications demand a low PAPR in terms of both the error performance and the strict restriction of the spectrum mask. In this letter, we propose a PAPR reduction method based on the modified active constellation extension for systems using SRRC filters. Results show that the proposed method substantially reduces the PAPR, and therefore it is applicable to satellite communications to improve the power efficiency at the transmitter.

In this letter, we present a low-complexity residual symbol timing offset (STO) estimation scheme in a long term evolution (LTE) downlink system. The proposed scheme is designed to estimate STO without a priori knowledge of cell-specific reference signals, which reduces the arithmetic complexity while maintaining a similar performance to the conventional algorithm.