IEICE TRANSACTIONS on Fundamentals
Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs
Summary :
I. O'Connor et al. have proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) to generate some logic functions by using the double-gate (DG) carbon nanotube (CNT) FETs which have the ambipolar property [1]. This DRDLC consists of seven transistors to generate 14 logic functions which do not include the XOR and XNOR functions. On the other hand, K. Jabeur et al. have proposed a DRDLC to generate the whole set of 16 logic functions including XOR and XNOR by adding 4 or 8 transistors to O'Connor's circuit [5]. In this letter, we propose a DRDLC, which consists of only seven transistors, to generate the whole set of 16 logic functions by using DG-CNTFETs. Finally, we show that the number of transistors can be reduced compared to the conventional DRDLC to generate 16 logic functions.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.7 pp.1642-1644
- Publication Date
- 2013/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.1642
- Type of Manuscript
- LETTER
- Category
- Circuit Theory
Authors
Manabu KOBAYASHI
Shonan Institute of Technology
Hiroshi NINOMIYA
Shonan Institute of Technology
Shigeyoshi WATANABE
Shonan Institute of Technology
Keyword
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Manabu KOBAYASHI, Hiroshi NINOMIYA, Shigeyoshi WATANABE, "Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 7, pp. 1642-1644, July 2013, doi: 10.1587/transfun.E96.A.1642.
Abstract: I. O'Connor et al. have proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) to generate some logic functions by using the double-gate (DG) carbon nanotube (CNT) FETs which have the ambipolar property [1]. This DRDLC consists of seven transistors to generate 14 logic functions which do not include the XOR and XNOR functions. On the other hand, K. Jabeur et al. have proposed a DRDLC to generate the whole set of 16 logic functions including XOR and XNOR by adding 4 or 8 transistors to O'Connor's circuit [5]. In this letter, we propose a DRDLC, which consists of only seven transistors, to generate the whole set of 16 logic functions by using DG-CNTFETs. Finally, we show that the number of transistors can be reduced compared to the conventional DRDLC to generate 16 logic functions.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.1642/_p
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@ARTICLE{e96-a_7_1642,
author={Manabu KOBAYASHI, Hiroshi NINOMIYA, Shigeyoshi WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs},
year={2013},
volume={E96-A},
number={7},
pages={1642-1644},
abstract={I. O'Connor et al. have proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) to generate some logic functions by using the double-gate (DG) carbon nanotube (CNT) FETs which have the ambipolar property [1]. This DRDLC consists of seven transistors to generate 14 logic functions which do not include the XOR and XNOR functions. On the other hand, K. Jabeur et al. have proposed a DRDLC to generate the whole set of 16 logic functions including XOR and XNOR by adding 4 or 8 transistors to O'Connor's circuit [5]. In this letter, we propose a DRDLC, which consists of only seven transistors, to generate the whole set of 16 logic functions by using DG-CNTFETs. Finally, we show that the number of transistors can be reduced compared to the conventional DRDLC to generate 16 logic functions.},
keywords={},
doi={10.1587/transfun.E96.A.1642},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1642
EP - 1644
AU - Manabu KOBAYASHI
AU - Hiroshi NINOMIYA
AU - Shigeyoshi WATANABE
PY - 2013
DO - 10.1587/transfun.E96.A.1642
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2013
AB - I. O'Connor et al. have proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) to generate some logic functions by using the double-gate (DG) carbon nanotube (CNT) FETs which have the ambipolar property [1]. This DRDLC consists of seven transistors to generate 14 logic functions which do not include the XOR and XNOR functions. On the other hand, K. Jabeur et al. have proposed a DRDLC to generate the whole set of 16 logic functions including XOR and XNOR by adding 4 or 8 transistors to O'Connor's circuit [5]. In this letter, we propose a DRDLC, which consists of only seven transistors, to generate the whole set of 16 logic functions by using DG-CNTFETs. Finally, we show that the number of transistors can be reduced compared to the conventional DRDLC to generate 16 logic functions.
ER -
English
