A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS
Summary :
This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.2 pp.365-371
- Publication Date
- 2007/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.2.365
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
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Takeshi UENO, Takafumi YAMAJI, Tetsuro ITAKURA, "A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 2, pp. 365-371, February 2007, doi: 10.1093/ietfec/e90-a.2.365.
Abstract: This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.2.365/_p
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@ARTICLE{e90-a_2_365,
author={Takeshi UENO, Takafumi YAMAJI, Tetsuro ITAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS},
year={2007},
volume={E90-A},
number={2},
pages={365-371},
abstract={This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.},
keywords={},
doi={10.1093/ietfec/e90-a.2.365},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 365
EP - 371
AU - Takeshi UENO
AU - Takafumi YAMAJI
AU - Tetsuro ITAKURA
PY - 2007
DO - 10.1093/ietfec/e90-a.2.365
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2007
AB - This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.
ER -
English
