Recently, the Doherty amplifier technique has been the focus of attention not only for base stations but also for mobile terminals because of its high power-added efficiency in the large back-off region. In this paper, we present a miniaturized Doherty power amplifier (PA) module for W-CDMA mobile terminals. The developed Doherty PA module consists of a 4-mm-square ceramic substrate (4.0 mm4.0 mm1.5 mm, alumina, dielectric constant = 8.8), a 1-mm-square GaAs MMIC (1.0 mm1.0 mm0.1 mm), and 0603-size SMD passive components. To miniaturize the module size, the optimal designed quarter-wavelength transmission lines, which are used for impedance conversion for carrier amplifier output and phase compensation for peak amplifier input, are embedded in the ceramic module substrate. Two GaAs HBTs for a carrier amplifier and a peak amplifier and base bias circuits for each amplifier are integrated onto a single-chip GaAs MMIC. Measurement results at 1950 MHz in a W-CDMA uplink signal indicate that 27 dBm of the maximum output power, 45% of the power-added efficiency (PAE), 11 dB of power gain, and 43% of PAE at 6 dB back-off, i.e. 24 dBm output power, are obtained with the developed Doherty PA. In other words, the PAE is improved from the theoretical PAE of a conventional class B amplifier, namely, from 23% to 43%. This is the smallest Doherty amplifier developed in the form of a module for mobile terminals.

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP₃) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP₃ of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.

A 10-GHz sub-harmonic Gilbert mixer is demonstrated in this paper using the 0.35 µm SiGe BiCMOS technology. The time-delay when the sub-harmonic LO (Local Oscillator) stage generates sub-harmonic LO signals is compensated by using fully symmetrical multiplier pairs. High RF-to-IF isolation and sub-harmonic LO Gilbert cell with excellent frequency response can be achieved by the elimination of the time-delay. The SiGe BiCMOS sub-harmonic micromixer exhibits 17 dB conversion gain, -74 dB 2LO-to-RF isolation, IP_{1 dB} of -20 dBm, and IIP₃ of -10 dBm. The measured double sideband noise figure is 16 dB from 100-kHz to 100-MHz because the SiGe bipolar device has very low 1/f noise corner.

Element value spread of an equal-ripple RC polyphase filter depends heavily on the order of zero assignment. To find the optimum design, we must conduct exhaustive design for all the possible zero assignments. This paper describes two circuit transformations on equal-ripple RC polyphase filters, which preserve their transfer functions, for reducing circuit design efforts. Proposed Method I exchanges (R,C) values to (1/C,1/R) for each stage. This gives a new circuit with different zero assignment for each stage of its original circuit. Method II flips over the original circuit and exchanges the resulting (R_i,C_i) values for (C_n-i+1,R_n-i+1) for each i-th stage. Those circuit transformations can reduce a number of circuit designs down to 1/4 of the straight-forward method. This considerably reduces a burden for exhaustive design for searching the minimum element value spread condition. Some design examples are given to illustrate the proposed methods.

This paper proposes a synthesis method of all low-voltage CMOS instantaneous-companding log domain integrators. The method is based on the exhaustive search of all low-voltage CMOS instantaneous-companding log domain integrators. All the integrators are derived from a general block diagram. A function of each block can be realized by any of a family of circuits and elemental circuits chosen from such families are combined to build an integrator. It is clarified that each family contains a few circuit topologies. All topologies of integrators including new ones are obtained from combinational procedure. Comparing characteristics of all generated integrators, ones satisfying required performances are found out.

This paper proposes a jitter tolerant continuous-time sigma-delta A-D converter structure as well as its design method. This method transforms a conventionally designed sigma-delta A-D converter into a jitter tolerant one. Jitter tolerance is provided by the modified feedback signal paths and a consequently inserted digital LPF. This method is applicable independently of a system order and the other specifications.

This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.

This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.

Band connections employed in active cancellation circuits for effective reduction of digital substrate noise are proposed. An almost-odd-symmetrical noise characteristic is utilized for canceling out noises. Advancing this idea, interlaced connections of four bands are also proposed. Excess cancellation by those bands is more effective for noise reduction in a guard ring than a cancellation by two bands. Use of L-shaped bands on the basis of the interlaced connection suppresses the noise more. Simulation and experimental results show that the proposed band connections reduce the noise.

Substrate-coupling equivalent circuits can be derived for arbitrary isolation structures by F-matrix computation. The derived netlist represents a unified impedance network among multiple sites on a chip surface as well as internal nodes of isolation structures and can be applied with SPICE simulation to evaluate isolation strengths. Geometry dependency of isolation attributes to layout parameters such as area, width, and location distance. On the other hand, structural dependency arises from vertical impurity concentration specific to p⁺/n⁺ diffusion and deep n-well. Simulation-based prototyping of isolation structures can include all these dependences and strongly helps establish an isolation strategy against high-frequency substrate coupling in a given technology. The analysis of isolation strength provided by p⁺/n⁺ guard ring, deep n-well guard ring as well as deep n-well pocket well explains S21 measurements performed on high-frequency test structures targeting 5 GHz bandwidth, that was formed in a 0.25-µm CMOS high frequency.

This paper presents a fast transient simulation method for power distribution networks (PDNs) of the PCB/Package. Because these PDNs are modeled as large-scale linear circuits consisting of a large number of RLC elements, it takes large costs to solve by conventional circuit simulators, such as SPICE. Our simulation method is based on the leapfrog algorithm, and can solve RLC circuits of PDNs faster than SPICE. Actual PDNs have frequency-dependent dispersions such as the skin-effect of conductors and the dielectric loss. To model these dispersions, more number of RLC elements are required, and circuit structures of these dispersion models are hard to solve by using the leapfrog algorithm. This paper shows that the circuit structures of dispersion models can be converted to suitable structures for the leapfrog algorithm. Further, in order to reduce the simulation time, our proposed method exploits parallel computation techniques. Numerical results show that our proposed method using single processing element (PE) enables a speedup of 20-100 times and 10 times compared to HSPICE and INDUCTWISE with the same level of accuracy, respectively. In a large-scale example with frequency-dependent dispersions, our method achieves over 94% parallel efficiency with 5PEs.

An effective way to boost power gain without noise figure degradation in a cascode low noise amplifier (LNA) is demonstrated at 4 GHz using 0.35 µm SiGe HBT technology. This approach maintains the same current consumption because a low-pass π-type LC matching network is inserted in the inter-stage of a conventional cascode LNA. 5 dB gain enhancement with no noise figure degradation at 4 GHz is observed in the SiGe HBT LNA with inter-stage matching.

A 5.2 GHz 1 dB conversion gain, IP_{1 dB} = -19 dBm and IIP₃= -9 dBm double quadrature Gilbert downconversion mixer with polyphase filters is demonstrated by using 0.35 µm SiGe HBT technology. The image rejection ratio is better than 47 dB when LO=5.17 GHz and IF is in the range of 15 MHz to 45 MHz. The Gilbert downconverter has four-stage RC-CR IF polyphase filters for the image rejection. Polyphase filters are also used to generate LO and RF quadrature signals around 5 GHz in the double quadrature downconverter.

Distortion analysis of nonlinear circuits is very important for designing analog integrated circuits and communication systems. In this letter, we propose an efficient frequency-domain approach for calculating frequency response curves, which is based on HB (harmonic balance) method combining with ABMs (Analog Behavior Models) of Spice. Firstly, nonlinear devices such as bipolar transistors and MOSFETs are transformed into the HB device modules executing the Fourier transformations. Using these modules, the determining equation of the HB method is formed by the equivalent sine-cosine circuit in the schematic form or net-list. It consists of the coupled resistive circuits, so that it can be efficiently solved by the DC analysis of Spice. In our algorithm, we need not to derive any troublesome circuit equations, and any kinds of the transformations.

Two versions of Krylov subspace order reduction techniques for VLSI interconnect reductions, including structure preserving reductions approach and adjoint networks approach, will be comparatively investigated. Also, we will propose a modified structure preserving reduction algorithm to speed up the projection construction in a linear order. The numerical experiment shows the high accuracy and low computational consumption of the modified method. In addition, it will be shown that the projection subspace generated from the structure-preserving approach and those from the adjoint networks approach are equivalent. Therefore, transfer functions of both reduced networks are identical.

We present theoretical foundations about error estimations of the global Krylov subspace techniques for multiple-inputs multiple-outputs (MIMO) Interconnect reductions. Analytical relationships between Lyapunov functions of the original interconnect network and those of the reduced system generated by the global Arnoldi algorithm will be developed. Under this framework, a new moment matching reduced network is proposed. Also, we will show that the reduced system can be expressed as the original network with some additive perturbations.

In D.O.A. estimation, identification of the signal and the noise subspaces plays an essential role. This identification process was traditionally achieved by the eigenvalue decomposition (EVD) of the spatial correlation matrix of observations or the generalized eigenvalue decomposition (GEVD) of the spatial correlation matrix of observations with respect to that of an observation noise. The framework based on the GEVD is not always an extension of that based on the EVD, since the GEVD is not applicable to the noise-free case which can be resolved by the framework based on the EVD. Moreover, they are not applicable to the case in which the spatial correlation matrix of the noise is singular. Recently, a quotient-singular-value-decomposition-based framework, that can be applied to problems with singular noise correlation matrices, is introduced for noise reduction. However, this framework also can not treat the noise-free case. Thus, we do not have a unified framework of the identification of these subspaces. In this paper, we show that a unified framework of the identification of these subspaces is realized by the concept of proper and improper eigenspaces of the spatial correlation matrix of the noise with respect to that of observations.

JPEG2000 compression standard considers a block of wavelet coefficients, called codeblock, as the smallest coding unit that being independently entropy-coded. In this paper, we propose a codeblock-based concealment technique for JPEG2000 images to mitigate missing codeblock due to packet loss in network transmission. The proposed method creates a single JPEG2000 codestream from an image that composed of several subsampled versions of the original image and transmit the codestream over a single channel.The technique then substitutes the affected codeblock in a subsampled image with a copy of the corresponding codeblock obtained from other subsampled images. Thus, it does not require an iterative processing, which is time consuming, to construct an estimated version of the lost data. Moreover, it is applicable for a large codeblock size and can be implemented either in wavelet or codestream domain. Simulation results confirm the effectiveness of the proposed method.

This paper is intended to provide an alternative approach for the design of FIR filters by using a Hopfield Neural Network (HNN). The proposed approach establishes the error function between the amplitude response of the desired FIR filter and the designed one as a Lyapunov energy function to find the HNN parameters. Using the framework of HNN, the optimal filter coefficients can be obtained from the output state of the network. With the advantages of local connectivity, regularity and modularity, the architecture of the proposed approach can be applied to the design of differentiators and Hilbert transformer with significantly reduction of computational complexity and hardware cost. As the simulation results illustrate, the proposed neural-based method is capable of achieving an excellent performance for filter design.

Buck, boost, and buck-boost converters constitute large class of dc-dc converters used in practice and are interesting nonlinear dynamical systems. It has been shown earlier that various nonlinear phenomena including subharmonics and chaos can be observed in these converters. In this paper we show that with the simplifying assumption that voltage regulation is achieved in high frequency modulation, a very simple dimensionless model can be derived that explains the dynamic phenomena in both continuous conduction mode as well as the discontinuous conduction mode. Using this model, we analyze some peculiar aspects of the dynamics in discontinuous conduction mode like the occurrence of superstable orbits.

In this paper, we propose CRadix sort, a new string sorting algorithm based on MSD radix sort. CRadix sort causes fewer cache misses than MSD radix sort by uniquely associating a small block of main memory called the key buffer to each key and temporarily storing a portion of each key into its corresponding key buffer. Experimental results in running time comparisons with other string sorting algorithms are provided for showing the effectiveness of CRadix sort.

This paper examines a system which is inspected at equally spaced points in time. We express the observed states of the system as a discrete time Markov chain with an absorbing state. It is assumed that the true state is certainly identified through inspection. After each inspection, one of three actions can be taken: Operation, repair, or replacement. We assume that the result of repair is uncertain. If repair is taken, we decide whether to inspect the system or not. When inspection is performed after completion of repair, we select an optimal action. After replacement, the system becomes new. We study the optimal maintenance policy which minimizes the expected total discounted cost for unbounded horizon. It is shown that, under reasonable conditions on the system's deterioration and repair laws and the cost structures, a control limit policy is optimal. We derive several valid properties for finding the optimal maintenance policy numerically. Furthermore, numerical analysis is conducted to show our theoretical results could hold under weaker conditions.

Both mutual authentication and generation of session keys can be accomplished by an authenticated key exchange (AKE) protocol. Let us consider the following situation: (1) a client, who communicates with many different servers, remembers only one password and has insecure devices (e.g., mobile phones or PDAs) with very-restricted computing power and built-in memory capacity; (2) the counterpart servers have enormous computing power, but they are not perfectly secure against various attacks (e.g., virus or hackers); (3) neither PKI (Public Key Infrastructures) nor TRM (Tamper-Resistant Modules) is available. The main goal of this paper is to provide security against the leakage of stored secrets as well as to attain high efficiency on client's side. For those, we propose an efficient and leakage-resilient RSA-based AKE (RSA-AKE) protocol suitable for the above situation whose authenticity is based on password and another secret. In the extended model where an adversary is given access to the stored secret of client, we prove that its security of the RSA-AKE protocol is reduced tightly to the RSA one-wayness in the random oracle model. We also show that the RSA-AKE protocol guarantees several security properties (e.g., security of password, multiple sever scenario with only one password, perfect forward secrecy and anonymity). To our best knowledge, the RSA-AKE protocol is the most efficient, in terms of both computation costs of client and communication costs, over the previous AKE protocols of their kind (using password and RSA).

This paper investigates the fixed-rate and fixed-distortion lossy coding problems of individual sequences subject to the subadditive distortion measure. The fixed-rate and fixed-distortion universal lossy coding schemes based on the complexity of the sequence are proposed. The obtained coding theorems reveal that the optimal distortion (resp. rate) attainable by the fixed-rate (resp. fixed-distortion) lossy coding is equal to the optimal average distortion (resp. rate) with respect to the overlapping empirical distribution of the given sequence. Some connections with the lossy coding problem of ergodic sources are also investigated.

This paper proposes a butterfly structure for Viterbi decoders, which works for convolutional codes of all rates k/n. The proposed butterfly structure can exploit the inherent symmetry of trellis branches, so that only some branch metrics need to be computed, while the others can be derived from the computed branches. Consequently, the computational complexity of the Viterbi decoder can be significantly reduced without any error performance loss. The applicability of the butterfly structure is validated by the best codes of rates 1/2, 2/3, and 3/4. Most of the best codes can apply the butterfly structure to reduce their branch metric computation complexity by a factor of 2 or 4. This study also reports a number of new codes with high branch symmetry under the symmetry consideration. Their branch metric computation can be reduced by a factor of 4, 8 or 16 with the similar performance to the best codes.

In this paper, novel hardware sharing architectures are proposed for realizations of fast 44 and 88 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 44 and 88 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 44 and individual 88 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125 MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.

This paper deals with a design problem of an observer-based robust preview control system for uncertain discrete-time systems. In this approach, we adopt 2-stage design scheme and we derive an observer-based robust controller with integral and preview actions such that a disturbance attenuation level is satisfactorily small for allowable uncertainties.

We propose a stability-guaranteed horizon size (SgHS) for stabilizing receding horizon control (RHC). It is shown that the proposed SgHS can be represented explicitly in terms of the known parameters of the given system model and is independent of the terminal weighting matrix in the cost function. The proposed SgHS is validated via a numerical example.

We study on the security proof of the improved efficient-Rabin (ERabin) scheme and the F-FDHS scheme. First, we show that the security theorem of the improved ERabin scheme is not correct, and then provide a correct theorem for it. Second, we show that the security theorem of the F-FDHS scheme lacks an assumption. Finally, we present a way to modify the improved ERabin scheme and the F-FDHS scheme.

Decoding performance of LDPC (Low-Density Parity-Check) codes is highly dependent on the degree distributions of the Tanner graphs which define the LDPC codes. We compare two LDPC code ensembles, one has a uniform degree distribution and the other a non-uniform one over a BEC (Binary Erasure Channel) and a BSC (Binary Symmetric Channel) thorough DE (Density Evolution). We then derive sufficient conditions on the erasure probability of a BEC and the error probability of a BSC, under which the LDPC code ensembles with uniform degree distributions outperform those with non-uniform degree distributions.

In our previous work, we have proposed a method for constructing ZCZ sequence sets. The method proposed by the previous work is based on perfect sequences and unitary matrices. This method can generate ZCZ sequence sets which possess a good feature concerning the length of zero-correlation zones. In this letter, we propose a new method for constructing ZCZ sequence sets by improving the previous method. The proposed method can generate new ZCZ sequence sets which can not be obtained from the previous method. These ZCZ sequence sets also possess the good feature concerning the length of zero-correlation zones.

A secure and efficient route discovery protocol is proposed for ad hoc networks, where only one-way hash functions are used to authenticate nodes in the ROUTE REQUEST, while additional public-key cryptography is used to guard against active attackers disguising a node in the ROUTE REPLY.