IEICE TRANSACTIONS on Fundamentals
Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier
Summary :
We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.2 pp.317-325
- Publication Date
- 2007/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.2.317
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
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Takao KIHARA, Guechol KIM, Masaru GOTO, Keiji NAKAMURA, Yoshiyuki SHIMIZU, Toshimasa MATSUOKA, Kenji TANIGUCHI, "Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 2, pp. 317-325, February 2007, doi: 10.1093/ietfec/e90-a.2.317.
Abstract: We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.2.317/_p
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@ARTICLE{e90-a_2_317,
author={Takao KIHARA, Guechol KIM, Masaru GOTO, Keiji NAKAMURA, Yoshiyuki SHIMIZU, Toshimasa MATSUOKA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier},
year={2007},
volume={E90-A},
number={2},
pages={317-325},
abstract={We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.},
keywords={},
doi={10.1093/ietfec/e90-a.2.317},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 317
EP - 325
AU - Takao KIHARA
AU - Guechol KIM
AU - Masaru GOTO
AU - Keiji NAKAMURA
AU - Yoshiyuki SHIMIZU
AU - Toshimasa MATSUOKA
AU - Kenji TANIGUCHI
PY - 2007
DO - 10.1093/ietfec/e90-a.2.317
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2007
AB - We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.
ER -
English
