IEICE TRANSACTIONS on Fundamentals
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High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA
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- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.0 No.0 pp.0-0
- Publicized
- 2024/05/28
- DOI
- 10.1587/10.1587/transfun.2023EAP1135
- Type of Manuscript
- PAPER
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Meiting XUE, Wenqi WU, Jinfeng LUO, Yixuan ZHANG, Bei ZHAO, "High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA" in IEICE TRANSACTIONS on Fundamentals,
vol. , no. 0, pp. 0-0, January , doi: 10.1587/10.1587/transfun.2023EAP1135.
Abstract:
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2023EAP1135/_advpub_f
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@ARTICLE{2023EAP1135,
author={Meiting XUE, Wenqi WU, Jinfeng LUO, Yixuan ZHANG, Bei ZHAO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA},
year={},
volume={},
number={0},
pages={0-0},
abstract={},
keywords={},
doi={10.1587/10.1587/transfun.2023EAP1135},
ISSN={},
month={January},}
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TY - JOUR
TI - High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 0
EP - 0
AU - Meiting XUE
AU - Wenqi WU
AU - Jinfeng LUO
AU - Yixuan ZHANG
AU - Bei ZHAO
PY -
DO - 10.1587/10.1587/transfun.2023EAP1135
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL -
IS - 0
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January
AB -
ER -
English
