This paper presents a miniaturized dual-mode Doherty PA module applicable for an HPSK signal and an OFDM 64-QAM signal. Dual-mode operation with identical hardware is realized by introducing a bias switching technique, which changes bias conditions of amplifiers according to transmission signals, and employing dual-mode matching circuits, which are designed based on the results of load-pull measurements using an HPSK signal and an OFDM 64-QAM signal. The Doherty PA module consists of a Doherty stage and a gain stage. Two GaAs-HBTs for a Doherty stage and one GaAs-HBT for a gain stage are integrated onto a 1 mm-square single GaAs-MMIC. In the HPSK mode, maximum output power of 26.7 dBm, power added efficiency (PAE) of 41%, and power gain of 27 dB are obtained in the condition that adjacent channel leakage power ratio (ACLR) is under -38 dBc. In the OFDM 64-QAM mode, maximum output power of 21.0 dBm, PAE of 27%, and power gain of 28 dB are obtained under EVM < 3.0%. This is the first multi-mode Doherty PA module suitable for multi peak to average power ratio (PAPR) signals.

Recently, dynamic power supply voltage techniques, such as an Envelope Elimination and Restoration power amplifier (EER-PA) or Envelope-Tracking Power amplifier (ET-PA), have been attracting much attention because they can maintain high efficiency in large back-off region [1]-[6]. The dynamic power supply voltage techniques cause strong nonlinearity compared to a conventional power amplifier, hence a memoryless Digital Predistortion (DPD) technique is indispensable for these efficiency enhancement techniques. However, the performance of the memoryless DPD is degraded due to the frequency response of the envelope amplifier in the dynamic power supply voltage techniques [7]-[9]. In this paper, we clarify the degradation mechanisms of the memoryless DPD for the EER-PA due to the frequency response of the envelope amplifier based on the results of two-tone tests, and propose an analytical model for improving the performance of the memoryless DPD developed for the EER-PA. In addition, a prototype EER-PA is developed and we demonstrate that the residual distortion of the developed EER-PA with conventional memoryless DPD algorithm is compensated by the new algorithm based on the proposed analytical model. In the two-tone test, third-order intermodulation distortion (IMD3) with a tone spacing from 100 kHz to 4 MHz is improvement by up to 25 dB by the memoryless DPD algorithm based on the proposed model. Measured adjacent channel leakage power ratio (ACPR) of the developed EER-PA is improved from -22.5 dBc to -42.5 dBc in the OFDM signal test with 1.08 MHz bandwidth.

Step-edge Josephson junctions (SEJJs), which are made by YBa2Cu3O7 (YBCO) thin films on MgO (100) substrates with gentle step angle (below 40 degrees) have been successfully fabricated. The step-edge, with several angles on the MgO substrate, were made using photolithography and Ar ion beam etching, and then YBCO films were deposited on the step-edges by pulsed laser deposition method. The relationships between step-angles and I-V characteristics, microwave properties and structure of SEJJs were systematically investigated. Shapiro steps were clearly observed only in step-angle range between 10 and 30 degrees. Intermittence and hysteresis on the I-V characteristics were observed above 30 mA without effect from step-angles.

The optimum bias point for a drain mixer operating on low local oscillator (LO) power was investigated. The bias voltage dependence of the required LO power and the conversion gain in the drain mixer was clarified by a simplified nonlinear model which the drain current characteristics around knee voltage is approximated by two straight line segments. It was found that an optimum gate bias voltage Vgs exists for a given applied LO power, and the optimum gate bias voltage moves toward the pinch-off voltage as the injection LO power level decreases. In order to verify the variation of the optimum gate bias voltage, a 60 GHz MMIC drain mixer adopting the optimum gate bias voltage for low LO power level was fabricated. The fabricated drain mixer exhibited a conversion gain of 0 dB with the injection LO power level of 0 dBm. This value of 0 dBm is the best performance yet obtained for a 60 GHz MMIC drain mixer. The measured optimum gate bias voltage was near the pinch-off voltage. This result was in good agreement with the theoretical analysis. The LO power level of a drain mixer has been improved so that it is on a par with that of a gate mixer.

With the advent of 5G and external pressure to reduce greenhouse gas emissions, wireless transceivers with low power consumption are strongly desired for future cellular systems. At the same time, increased modulation order due to the evolution of cellular systems will force power amplifiers to operate at much larger output power back-off to prevent EVM degradation. This paper begins with an analysis of load modulation and asymmetrical Doherty amplifiers. Measurement results will show an apparent 60% efficiency plateau for modulated signals with a large peak-to-average power ratio (PAPR). To exceed this efficiency limitation, the second part of this paper focuses on a new amplification topology based on the amalgamation between Doherty and outphasing. Measurement results of the proposed Doherty-outphasing power amplifier (DOPA) will confirm the feasibility of the approach with a modulated efficiency greater than 70% measured at 10 dB output power back-off.

The authors have developed V-band high electron mobility transistor (HEMT) MMICs adopting benzo-cyclo-butene (BCB) thin-film layers on GaAs substrates. Since the BCB thin-film layers, which can change the thickness of arbitrary parts on a circuit, are used for these MMICs, both a thin-film microstrip (TFMS) line, offering the advantages of great flexibility in layout and small size, and a coplanar waveguide (CPW), offering the advantage of low loss, can be used according to the purpose of the MMIC. Here we introduce the four types of V-band MMICs that we fabricated: low noise amplifier (LNA), mixer, voltage controlled oscillator (VCO), and power amplifier (PA). The optimum transmission lines were chosen from the TFMS line and the CPW for these MMICs. Miniaturization of the LNA MMIC and the mixer MMIC were attained by adopting the TFMS line, whereas adoption of the CPW enabled the VCO MMIC to achieve high performance. These results indicate that it is important to choose the optimum transmission line according to the purpose of the circuit function for each MMIC. It was confirmed that these newly developed MMICs using the BCB thin-film dielectric layers are attractive for millimeter-wave applications.

Recently, the Doherty amplifier technique has been the focus of attention not only for base stations but also for mobile terminals because of its high power-added efficiency in the large back-off region. In this paper, we present a miniaturized Doherty power amplifier (PA) module for W-CDMA mobile terminals. The developed Doherty PA module consists of a 4-mm-square ceramic substrate (4.0 mm4.0 mm1.5 mm, alumina, dielectric constant = 8.8), a 1-mm-square GaAs MMIC (1.0 mm1.0 mm0.1 mm), and 0603-size SMD passive components. To miniaturize the module size, the optimal designed quarter-wavelength transmission lines, which are used for impedance conversion for carrier amplifier output and phase compensation for peak amplifier input, are embedded in the ceramic module substrate. Two GaAs HBTs for a carrier amplifier and a peak amplifier and base bias circuits for each amplifier are integrated onto a single-chip GaAs MMIC. Measurement results at 1950 MHz in a W-CDMA uplink signal indicate that 27 dBm of the maximum output power, 45% of the power-added efficiency (PAE), 11 dB of power gain, and 43% of PAE at 6 dB back-off, i.e. 24 dBm output power, are obtained with the developed Doherty PA. In other words, the PAE is improved from the theoretical PAE of a conventional class B amplifier, namely, from 23% to 43%. This is the smallest Doherty amplifier developed in the form of a module for mobile terminals.

A K-band monolithic driver amplifier with equalizer circuits has been developed. It is necessary for the equalizer circuit to be low losses in the high-frequency range and for its S21 values to increase as the operation frequency increases. In order to realize these features, it is desirable for the equalizer to have element location considering high-frequency current flows. In this paper, we present a novel low-loss, high-pass equalizer circuit layout that has superior characteristics in the high-frequency range. We used a high-pass filter as the equalizer circuit and performed a detailed evaluation of the high-frequency characteristics of the filter circuit test element groups (TEGs) for three layout types. It was found that the best filter circuit layout for the three types consisted of two capacitors and one resistor, placed with parallel connections. The resistor is located at the center and the capacitors are located at both sides of the resistor. This filter is called the CRC-type in this paper. An MMIC test sample, a K-band monolithic amplifier with CRC-type filter circuits, was fabricated. The amplifier had a gain of 21.6 dB, a Rollett stability factor K of 28.9, an input VSWR of 1.63, an output VSWR of 1.92, and a 1 dB compressed output power of 22.6 dBm at 26 GHz.