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[Author] Yuuki FUNAHASHI(2hit)

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  • A Proposal for Adopting the Frequency Response of an Envelope Amplifier with Memoryless DPD EER PA Model

    Takayuki KATO  Yoshinori KOGAMI  Yuuki FUNAHASHI  Atsushi YAMAOKA  Keiichi YAMAGUCHI  Yasuhiko TANABE  Jiafeng ZHOU  Kevin MORRIS  Gavin T. WATKINS  

     
    PAPER

      Vol:
    E95-C No:7
      Page(s):
    1163-1171

    Recently, dynamic power supply voltage techniques, such as an Envelope Elimination and Restoration power amplifier (EER-PA) or Envelope-Tracking Power amplifier (ET-PA), have been attracting much attention because they can maintain high efficiency in large back-off region [1]-[6]. The dynamic power supply voltage techniques cause strong nonlinearity compared to a conventional power amplifier, hence a memoryless Digital Predistortion (DPD) technique is indispensable for these efficiency enhancement techniques. However, the performance of the memoryless DPD is degraded due to the frequency response of the envelope amplifier in the dynamic power supply voltage techniques [7]-[9]. In this paper, we clarify the degradation mechanisms of the memoryless DPD for the EER-PA due to the frequency response of the envelope amplifier based on the results of two-tone tests, and propose an analytical model for improving the performance of the memoryless DPD developed for the EER-PA. In addition, a prototype EER-PA is developed and we demonstrate that the residual distortion of the developed EER-PA with conventional memoryless DPD algorithm is compensated by the new algorithm based on the proposed analytical model. In the two-tone test, third-order intermodulation distortion (IMD3) with a tone spacing from 100 kHz to 4 MHz is improvement by up to 25 dB by the memoryless DPD algorithm based on the proposed model. Measured adjacent channel leakage power ratio (ACPR) of the developed EER-PA is improved from -22.5 dBc to -42.5 dBc in the OFDM signal test with 1.08 MHz bandwidth.

  • Modified Algorithm on Maximum Detected Bit Flipping Decoding for High Dimensional Parity-Check Code

    Yuuki FUNAHASHI  Shogo USAMI  Ichi TAKUMI  Masayasu HATA  

     
    LETTER-Coding Theory

      Vol:
    E89-A No:10
      Page(s):
    2670-2675

    We have researched high dimensional parity-check (HDPC) codes that give good performance over a channel that has a very high error rate. HDPC code has a little coding overhead because of its simple structure. It has hard-in, maximum detected bit flipping (MDBF) decoding that has reasonable decoding performance and computational cost. In this paper, we propose a modified algorithm for MDBF decoding and compare the proposed MDBF decoding with conventional hard-in decoding.