Recently, dynamic power supply voltage techniques, such as an Envelope Elimination and Restoration power amplifier (EER-PA) or Envelope-Tracking Power amplifier (ET-PA), have been attracting much attention because they can maintain high efficiency in large back-off region [1]-[6]. The dynamic power supply voltage techniques cause strong nonlinearity compared to a conventional power amplifier, hence a memoryless Digital Predistortion (DPD) technique is indispensable for these efficiency enhancement techniques. However, the performance of the memoryless DPD is degraded due to the frequency response of the envelope amplifier in the dynamic power supply voltage techniques [7]-[9]. In this paper, we clarify the degradation mechanisms of the memoryless DPD for the EER-PA due to the frequency response of the envelope amplifier based on the results of two-tone tests, and propose an analytical model for improving the performance of the memoryless DPD developed for the EER-PA. In addition, a prototype EER-PA is developed and we demonstrate that the residual distortion of the developed EER-PA with conventional memoryless DPD algorithm is compensated by the new algorithm based on the proposed analytical model. In the two-tone test, third-order intermodulation distortion (IMD3) with a tone spacing from 100 kHz to 4 MHz is improvement by up to 25 dB by the memoryless DPD algorithm based on the proposed model. Measured adjacent channel leakage power ratio (ACPR) of the developed EER-PA is improved from -22.5 dBc to -42.5 dBc in the OFDM signal test with 1.08 MHz bandwidth.
Takayuki KATO
Yoshinori KOGAMI
Yuuki FUNAHASHI
Atsushi YAMAOKA
Keiichi YAMAGUCHI
Yasuhiko TANABE
Jiafeng ZHOU
Kevin MORRIS
Gavin T. WATKINS
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Takayuki KATO, Yoshinori KOGAMI, Yuuki FUNAHASHI, Atsushi YAMAOKA, Keiichi YAMAGUCHI, Yasuhiko TANABE, Jiafeng ZHOU, Kevin MORRIS, Gavin T. WATKINS, "A Proposal for Adopting the Frequency Response of an Envelope Amplifier with Memoryless DPD EER PA Model" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 7, pp. 1163-1171, July 2012, doi: 10.1587/transele.E95.C.1163.
Abstract: Recently, dynamic power supply voltage techniques, such as an Envelope Elimination and Restoration power amplifier (EER-PA) or Envelope-Tracking Power amplifier (ET-PA), have been attracting much attention because they can maintain high efficiency in large back-off region [1]-[6]. The dynamic power supply voltage techniques cause strong nonlinearity compared to a conventional power amplifier, hence a memoryless Digital Predistortion (DPD) technique is indispensable for these efficiency enhancement techniques. However, the performance of the memoryless DPD is degraded due to the frequency response of the envelope amplifier in the dynamic power supply voltage techniques [7]-[9]. In this paper, we clarify the degradation mechanisms of the memoryless DPD for the EER-PA due to the frequency response of the envelope amplifier based on the results of two-tone tests, and propose an analytical model for improving the performance of the memoryless DPD developed for the EER-PA. In addition, a prototype EER-PA is developed and we demonstrate that the residual distortion of the developed EER-PA with conventional memoryless DPD algorithm is compensated by the new algorithm based on the proposed analytical model. In the two-tone test, third-order intermodulation distortion (IMD3) with a tone spacing from 100 kHz to 4 MHz is improvement by up to 25 dB by the memoryless DPD algorithm based on the proposed model. Measured adjacent channel leakage power ratio (ACPR) of the developed EER-PA is improved from -22.5 dBc to -42.5 dBc in the OFDM signal test with 1.08 MHz bandwidth.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1163/_p
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@ARTICLE{e95-c_7_1163,
author={Takayuki KATO, Yoshinori KOGAMI, Yuuki FUNAHASHI, Atsushi YAMAOKA, Keiichi YAMAGUCHI, Yasuhiko TANABE, Jiafeng ZHOU, Kevin MORRIS, Gavin T. WATKINS, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Proposal for Adopting the Frequency Response of an Envelope Amplifier with Memoryless DPD EER PA Model},
year={2012},
volume={E95-C},
number={7},
pages={1163-1171},
abstract={Recently, dynamic power supply voltage techniques, such as an Envelope Elimination and Restoration power amplifier (EER-PA) or Envelope-Tracking Power amplifier (ET-PA), have been attracting much attention because they can maintain high efficiency in large back-off region [1]-[6]. The dynamic power supply voltage techniques cause strong nonlinearity compared to a conventional power amplifier, hence a memoryless Digital Predistortion (DPD) technique is indispensable for these efficiency enhancement techniques. However, the performance of the memoryless DPD is degraded due to the frequency response of the envelope amplifier in the dynamic power supply voltage techniques [7]-[9]. In this paper, we clarify the degradation mechanisms of the memoryless DPD for the EER-PA due to the frequency response of the envelope amplifier based on the results of two-tone tests, and propose an analytical model for improving the performance of the memoryless DPD developed for the EER-PA. In addition, a prototype EER-PA is developed and we demonstrate that the residual distortion of the developed EER-PA with conventional memoryless DPD algorithm is compensated by the new algorithm based on the proposed analytical model. In the two-tone test, third-order intermodulation distortion (IMD3) with a tone spacing from 100 kHz to 4 MHz is improvement by up to 25 dB by the memoryless DPD algorithm based on the proposed model. Measured adjacent channel leakage power ratio (ACPR) of the developed EER-PA is improved from -22.5 dBc to -42.5 dBc in the OFDM signal test with 1.08 MHz bandwidth.},
keywords={},
doi={10.1587/transele.E95.C.1163},
ISSN={1745-1353},
month={July},}
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TY - JOUR
TI - A Proposal for Adopting the Frequency Response of an Envelope Amplifier with Memoryless DPD EER PA Model
T2 - IEICE TRANSACTIONS on Electronics
SP - 1163
EP - 1171
AU - Takayuki KATO
AU - Yoshinori KOGAMI
AU - Yuuki FUNAHASHI
AU - Atsushi YAMAOKA
AU - Keiichi YAMAGUCHI
AU - Yasuhiko TANABE
AU - Jiafeng ZHOU
AU - Kevin MORRIS
AU - Gavin T. WATKINS
PY - 2012
DO - 10.1587/transele.E95.C.1163
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2012
AB - Recently, dynamic power supply voltage techniques, such as an Envelope Elimination and Restoration power amplifier (EER-PA) or Envelope-Tracking Power amplifier (ET-PA), have been attracting much attention because they can maintain high efficiency in large back-off region [1]-[6]. The dynamic power supply voltage techniques cause strong nonlinearity compared to a conventional power amplifier, hence a memoryless Digital Predistortion (DPD) technique is indispensable for these efficiency enhancement techniques. However, the performance of the memoryless DPD is degraded due to the frequency response of the envelope amplifier in the dynamic power supply voltage techniques [7]-[9]. In this paper, we clarify the degradation mechanisms of the memoryless DPD for the EER-PA due to the frequency response of the envelope amplifier based on the results of two-tone tests, and propose an analytical model for improving the performance of the memoryless DPD developed for the EER-PA. In addition, a prototype EER-PA is developed and we demonstrate that the residual distortion of the developed EER-PA with conventional memoryless DPD algorithm is compensated by the new algorithm based on the proposed analytical model. In the two-tone test, third-order intermodulation distortion (IMD3) with a tone spacing from 100 kHz to 4 MHz is improvement by up to 25 dB by the memoryless DPD algorithm based on the proposed model. Measured adjacent channel leakage power ratio (ACPR) of the developed EER-PA is improved from -22.5 dBc to -42.5 dBc in the OFDM signal test with 1.08 MHz bandwidth.
ER -