The 1-bit digital radio frequency (DRF) transmitter using a band-pass delta-sigma modulator (BP-DSM) can output a radio frequency (RF) signal carrying a binary data stream with a constant data rate regardless of the carrier frequency, which makes it possible to transmit RF signals over digital optical links with a constant bit rate. However, the optical link requires a line coding, such as 8B10B or 64B66B, to constrain runlength and disparity, and the line coding corrupts the DRF power spectrum owing to additional or encoded data. This paper proposes a new line coding for BP-DSM, which is able to control the runlength and the disparity of the 1-bit data stream by adding a notch filter to the BP-DSM that suppresses the low frequency components. The notch filter stimulates the data change and balances the direct current (DC) components. It is demonstrated that the proposed line coding shortens the runlength from 50 bits to less than 8 bits and reduces the disparity from several thousand bits to 5 bits when the 1-bit DRF transmitter outputs an LTE signal with 5 MHz bandwidth, when using carrier frequencies from 0.5GHz to 2GHz and an output power variation of 60dB.

The 1-bit band-pass delta-sigma modulator (BP-DSM) achieves high resolution if it uses an oversampling technique. This method can generate concurrent dual-band RF signals from a digitally modulated signal using a 1-bit digital pulse train. It was previously reported that the adjacent channel leakage ratio (ACLR) deteriorates owing to the asymmetrical waveform created by the pulse transition mismatch error of the rising and falling waveforms in the time domain and that the ACLR can be improved by distortion compensation. However, the reported distortion compensation method can only be performed for single-band transmission, and it fails to support multi-band transmission because the asymmetrical waveform compensated signal extends over a wide frequency range and is itself a harmful distortion outside the target band. Unfortunately, the increase of out-of-band power causes the BP-DSM unstable. We therefore propose a distortion compensator for a concurrent dual-band 1-bit BP-DSM that consists of a noise transfer function with a quasi-elliptic filter that can control the out-of-band gain frequency response against out-of-band oscillation. We demonstrate that dual-band LTE signals, each with 40MHz (2×20MHz) bandwidth, at 1.5 and 3.0GHz, can be compensated concurrently for spurious distortion under various combinations of rising and falling times and ACLR of up to 48dB, each with 120MHz bandwidth, including the double sided adjacent channels and next adjacent channels, is achieved.

We propose an architecture for a 1-bit band-pass delta-sigma modulator (BP-DSM) that outputs concurrent multiband RF signals. The proposed BP-DSM consists of parallel bandpass filters (BPFs) in the feedback loop to suppress the quantization noise at each target frequency band while maintaining the stability. Each BPF is based on second-order parallel infinite impulse response (IIR) filters. This architecture can unify and reconfigure the split BPFs according to the number of bands. The architecture complexity is proportional to the bandwidth of each RF signal and is independent of the carrier spacing between the bands. The conventional architecture of a concurrent multiband digital modulator, reported previously, has multiple input ports to the dedicated BPF at each band and so it cannot be efficiently integrated. Measurements show that the proposed architecture is feasible for transmitting a concurrent dual-band and a triple-band by changing the 1-bit digital data stream while keeping a data transmission rate of 10Gb/s. We demonstrate that the proposed architecture outputs the signal with LTE intra-band and inter-band carrier aggregation on 0.8GHz, 2.1GHz and 3.5GHz, each with 40MHz bandwidth in 120MHz aggregated bandwidth, whose bandwidth surpasses the bandwidth with carrier aggregation of LTE-A up to 100MHz. Adjacent channel leakage ratios of -49dBc and -46dBc are achieved at 3.5GHz in the concurrent dual-band and triple-band, respectively.

This paper proposes 1-bit feedforward distortion compensation for digital radio frequency conversion (DRFC) with 1-bit bandpass delta-sigma modulation (BP-DSM). The 1-bit BP-DSM allows direct RF signal transmission from a digitally modulated signal. However, it has been previously reported that 1-bit digital pulse trains with non-ideal rectangle waveform cause spectrum regrowth. The proposed architecture adds a feedforward path with another 1-bit BP-DSM and so can cancel out the distortion components at any target carrier frequency. Both the main signal and the distortion compensation signal are 1-bit digital pulse trains and so no additional analog RF circuit is required for distortion compensation. Simulation results show that the proposed method holds the adjacent channel leakage ratio to 60dB for LTE signal transmission. A prototype of the proposed 1-bit DRFC with an additional 1-bit BP-DSM in the feedforward path shows an ACLR of 50dB, 4dB higher than that of the conventional 1-bit DRFC.

We present our design and operation of a 6-bit quasi-triangle voltage waveform generator comprising three circuit blocks; an improved variable Pulse Number Multiplier (variable-PNM), a Code Generator (CG), and a Double-Flux-Quantum Amplifier (DFQA). They are integrated into a single chip using a niobium Josephson junction technology. While the multiplication factor of our previous m-bit variable-PNM was limited between 2m-1 and 2m, that of the improved one is extended between 1 and 2m. Correct operations of the 6-bit variable-PNM are confirmed in low-speed testing with respect to the codes from the CG, whereas generation of a 6-bit, 0.20mVpp quasi-triangle voltage waveform is demonstrated with the 10-fold DFQA in high-speed testing.

This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.

This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5TCLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.

An efficient way to optimize the hardware consumption in a low-voltage ΔΣ modulator for D/A converters is described. The modulator employs a ROM selection scheme for multiplications and the new buffer-and-routing ROM structure to minimize the hardware consumption. Furthermore, a guideline of the power-delay-and-area product (PDAP) for compelling issues such as power dissipation, delay time, and chip area consumption in the modern digital-circuit design is proposed. After the validity of the concept has been proved in comparison with that of the conventional guideline of the power-delay product in several behavioral blocks, it was employed in the circuit design. Fabricated in a standard digital 0.35-µm CMOS technology, the modulator achieves a signal-to-noise ratio (SNR) of 96 dB with an oversampling ratio of 256 under the supply of 2.0 V.

We present a digital double relaxation oscillation SQUID (DROS) with a digital flux-locked-loop (FLL) circuit consisting of an up/down counter and a digital-to-analog (D/A) converter. The up/down counter was designed using 4 jucntion logic (4JL) gates operated with a 2-phase power system. The D/A converter was designed using an R-2R ladder-type D/A converter. We simulated the dynamic behavior of the digital DROS with a digital FLL circuit combined with the 5-bit ripple up/down counter and the D/A converter. Simulation results show correct flux-locked behavior and a high slew rate of 107Φ0/s for the digital DROS.

This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 µm CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.

High-end graphic systems with 3 million pixels require 8-bit D/A converters with more than 300-MS/s conversion rate. Furthermore, D/A converters need to operate with low supply voltage when they are integrated with large-scale digital circuits on a harf-micron CMOS process. This paper describes a 350-MS/s 8-bit CMOS D/A converter with 3.3-V power supply. A current source circuit with a delayed driving scheme is developed. This driving scheme reduces a fluctuation of internal node voltage of the current source circuit and high-speed swiching is realized. In addition to this driving scheme, two stages of latches are inserted into matrix decoder for reducing glitch energy and for enhancing decoding speed. The D/A converter is fabricated in a 0.5-µm CMOS process with single poly-silicon layer and double aluminum layers. Its settling time is less than 2.4 ns and it successfully operates at 350 MS/s.

We describe low supply voltage analog circuit techniques for voice- and audio-band interfaces. These techniques can lower the supply voltage to 1 V, which is the voltage of a one-NiCd-cell battery. We have applied them in a swingsuppression noise-shaping method, and using this method, have fabricated A/D and D/A converters for the voice and audio bands. These converters operate with a 1 V power supply and have 13-bit and 17-bit accuracy in the audio-band and power consumption of about 1 mW. This performance proves that our techniques are sufficient for baseband analog interfaces.

It has become an important subject to realize a high-speed D/A converter with low supply voltage. This paper discusses a 10 bit 50 MS/s CMOS D/A converter with 2.7 V power supply. Reduction of the supply voltage is achieved by developing "saturation-linear" biasing technique in current sources. In this scheme, a grounded transistor in cascode configuration is biased in linear region. High conversion rate is obtained by driving this grounded transistor directly. A charging transistor is also introduced into the current source for accelerating the settling time. The D/A converter is fabricated in a 1 µm CMOS process without using optional process steps. It successfully operates at 50 MS/s with 2.7 V power supply. The circuit techniques discussed here can be easily introduced into half-micron D/A converters.

A current source with current switches (switched current source) is widely used in various analog ICs. One of its typical application is data converters. This paper describes an analysis of the transient behavior of a switched current source. The analysis has clarified conditions and causes of overshooting in the output waveform. The analysis also clarifies dependence of the settling time on parameters. The waveform heavily depends on time constant and initial charge at the internal node where current source and current switch are connected. They can cause the overshooting and limit the settling time. A phenomenon of acceleration of the settling time and an influence of the charge coupling through current switches are also discussed. A chart mentioned in this paper is useful for the initial design and the improvement of switched current sources.