IEICE TRANSACTIONS on Electronics
Compact Realization of Phase-Locked Loop Using Digital Control
Summary :
This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 µm CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.4 pp.544-549
- Publication Date
- 1997/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
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Masanori IZUMIKAWA, Masakazu YAMASHINA, "Compact Realization of Phase-Locked Loop Using Digital Control" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 4, pp. 544-549, April 1997, doi: .
Abstract: This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 µm CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_4_544/_p
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@ARTICLE{e80-c_4_544,
author={Masanori IZUMIKAWA, Masakazu YAMASHINA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Compact Realization of Phase-Locked Loop Using Digital Control},
year={1997},
volume={E80-C},
number={4},
pages={544-549},
abstract={This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 µm CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - Compact Realization of Phase-Locked Loop Using Digital Control
T2 - IEICE TRANSACTIONS on Electronics
SP - 544
EP - 549
AU - Masanori IZUMIKAWA
AU - Masakazu YAMASHINA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1997
AB - This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 µm CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.
ER -
English
