A serial ATA PHY fabricated in a 0.15-µm CMOS process performs the serial ATA operation in an asynchronous transition by using large variation in the reference clock. This technique calibrates a transmission signal frequency by utilizing the received signal. This is achieved by calibrating the divide ratio of a spread-spectrum clock generator (SSCG). This technique enables a serial ATA PHY to use reference oscillators with a production-frequency tolerance of less than 400ppm, i.e., higher than the permissible TX frequency variations (i.e., 350ppm). The calibrated transmission signal achieved a total jitter of 3.9ps.

A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was realized in 0.13,$mu$m CMOS technology. It consists of an analog PLL, a harmonic-rejection mixer and injection-locked frequency doublers to cover the whole 6--18,GHz frequency range. To achieve a low phase noise performance, a sub-sampling PLL with non-dividers was employed. The synthesizer can achieve phase noise $-$113.7,dBc/Hz@100,kHz in the best case and the reference spur is below $-$60,dBc. The core of the synthesizer consumes about 110,mA*1.2,V.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.

A new charge pump is proposed which provides improved jitter characteristics for a phase-locked loop (PLL). The PLL with the proposed charge pump is implemented with 0.6 µm CMOS technology. The measured RMS output jitter is as much as 28% smaller than that of a PLL with a previously reported charge pump structure.

In this paper, we analyze overload and stability in the charge-pump phase locked loop (PLL). We propose a new computational model that can be applied for the precise estimation of the physical limits of charge-pump, the leakage current of loop filter and waveform distortion of charge-pump PLL operating in high speed. We derive the exact mathematical expressions of the parameters describing the steady-state behavior of the PLL as well as the transient-state behavior. Performance comparisons with the conventional model are provided through numerical results. Algorithms for approximate analysis is also provided. The new model is particularity useful for analyzing the cases that the charge-pump PLL operates in high- speed or the loop filter has large leakage current.

This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 µm CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.

A 3.2 GHz, 50 mW, 1 V, GaAs clock pulse generator (CG) based on a phase-locked loop (PLL) circuit has been designed for use as an on-chip clock generator in future high speed processor LSIs. 0.5 µm GaAs MESFET and DCFL circuit technologies have been used for the CG, which consists of 224 MESFETs. An "enhanced charge-up current" inverter has been specially designed for a low power and high speed voltage controlled oscillator (VCO). In this new inverter, a voltage controlled dMESFET is combined in parallel with the load dMESFET of a conventional DCFL inverter. This voltage controlled dMESFET produces an additional charge-up current resulting in the new VCO obtaining a much higher oscillation frequency than that of a ring oscillator produced with a conventional inverter. With a single 1 V power supply (Vdd), SPICE calculation results showed that the VCO tuning range was 2.25 GHz to 3.65 GHz and that the average VCO gain was approximately 1.4 GHz/V in the range of a control voltage (Vc) from 0 to 1 V. Simulation also indicated that at a Vdd of 1 V the CG locked on a 50 MHz external clock and generated a 3.2 GHz internal clock (=50 MHz64). The jitter and power dissipation of the CG at 3.2 GHz oscillation and a Vdd of 1 V were less than 8.75 psec and 50 mW, respectively. The typical lock range was 2.90 GHz to 3.59 GHz which corresponded to a pull-in range of 45.3 MHz to 56.2 MHz.