This paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.

A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.

As devices continue to shrink, the parameter shift due to process variation and aging effects has an increasing impact on the circuit yield and reliability. However, predicting how long a circuit can maintain its design yield above the design specification is difficult because the design yield changes during the aging process. Moreover, performing Monte Carlo (MC) simulation iteratively during aging analysis is infeasible. Therefore, most existing approaches ignore the continuity during simulations to obtain high speed, which may result in accumulation of extrapolation errors with time. In this paper, an incremental simulation technique is proposed for lifetime yield analysis to improve the simulation speed while maintaining the analysis accuracy. Because aging is often a gradual process, the proposed incremental technique is effective for reducing the simulation time. For yield analysis with degraded performance, this incremental technique also reduces the simulation time because each sample is the same circuit with small parameter changes in the MC analysis. When the proposed dynamic aging sampling technique is employed, 50× speedup can be obtained with almost no decline accuracy, which considerably improves the efficiency of lifetime yield analysis.

In the nanometer era, the power integrity problem has become one of the critical issues. Although checking this problem earlier can speed up the analysis, not so many tools are available now due to the limited design information at high levels. Most existing approaches at gate level require extra information of the cell library, which may require extra characterization efforts while migrating to new cell libraries. Therefore, an analytical approach is proposed in this paper to dynamically estimate the supply current waveforms at gate level using existing library information only, even for sequential circuits. The experimental results have shown that the estimation errors of such a quick approach are only 10% compared to HSPICE results.

This study develops a form of digital baseband Intra-Body communication for wideband transmission. A simplified circuit model of signal and noise is constructed to analyze the contribution of the high pass filter function of the electrostatic coupling Intra-Body communication system to wideband digital transmission in electrostatic coupling Intra-Body communication. A unit step function is presented to determine the maximum high pass 3 dB pole that can ensure favorable signal quality in a baseband Intra-Body communication system. Body noise is measured to estimate the range of the high pass 3 dB pole with good Signal to Noise Ratio. A 3.3 Volt battery-powered FPGA is experimentally implemented to confirm the feasibility of the wideband Intra-Body communication system. The experimental results indicate that the digital baseband Intra-Body communication system supports a data rate of more than 16MPS.

In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance (CDC) into the real power consumption of pattern pairs but still has high accuracy. In order to reduce the table size, we collect those pattern pairs with similar CDC values to be a group and only set an entry in the lookup table for each group. The proposed dynamic grouping process can automatically increase the entries of the lookup tables to cover the current CDC distribution of designs during the power characterization process. In order to improve the efficiency of characterization process, the Monte Carlo approach is used during the estimation for the average power of each group to skip the samples that will not increase the accuracy too much. After the power model of a circuit is built, the average power consumption for any test sequence can be estimated easily. The experimental result shows that the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using this lookup table.

In this study, we use the deconvolution of a square test stimulus to replace a series of sinusoidal test waveforms with different frequencies to simplify the measurement of human body impedance. The average biological impedance of body parts is evaluated by constructing a frequency response of the equivalent human body system. Only two stainless-steel electrodes are employed in the measurement and evaluation.

This study employs a simple measurement methodology that is based on the de-convolution of a square test stimulus to measure the transmission characteristics of the human body channel in an electrostatic-coupling intra body communication system. A battery-powered square waveform generator was developed to mimic the electrostatic-coupling intra body communication system operating in the environment of the ground free. The measurement results are then confirmed using a reliable measuring method (single tone) and spectral analysis. The results demonstrate that the proposed measurement approach is valid for up to 32.5 MHz, providing a data rate of over 16 Mbps.

For large circuits, vector compaction techniques could provide a faster solution for power estimation with reasonable accuracy. Because traditional sampling approach will incur useless transitions between every sampled pattern pairs after they are concatenated into a single sequence for simulation, we proposed a vector compaction method with grouping and single-sequence consecutive sampling technique to solve this problem. However, it is very possible that we cannot find a perfect consecutive sequence without any undesired transitions. In such cases, the compaction ratio of the sequence length may not be improved too much. In this paper, we propose an efficient approach to relax the limitation a little bit such that multiple consecutive sequences are allowed. We also propose an algorithm to reduce the number of sequences instead of setting the number as one to find better solutions for vector compaction problem. As demonstrated in the experimental results, the average compaction ratio and speedup can be significantly improved by using this new approach.

Embedded memories have been used extensively in modern SoC designs. In order to estimate the power consumption of an entire design correctly, an accurate memory power models are needed. However, the memory power model that is commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effects with scaling capability. The proposed approach is very useful to be combined with the memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into the existing power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.

In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.