IEICE TRANSACTIONS on Fundamentals
An Efficient Approach to Build Accurate Behavioral Models of PLL Designs
Summary :
In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.2 pp.391-398
- Publication Date
- 2006/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.2.391
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Keyword
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Chin-Cheng KUO, Yu-Chien WANG, Chien-Nan Jimmy LIU, "An Efficient Approach to Build Accurate Behavioral Models of PLL Designs" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 2, pp. 391-398, February 2006, doi: 10.1093/ietfec/e89-a.2.391.
Abstract: In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.2.391/_p
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@ARTICLE{e89-a_2_391,
author={Chin-Cheng KUO, Yu-Chien WANG, Chien-Nan Jimmy LIU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Efficient Approach to Build Accurate Behavioral Models of PLL Designs},
year={2006},
volume={E89-A},
number={2},
pages={391-398},
abstract={In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.},
keywords={},
doi={10.1093/ietfec/e89-a.2.391},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - An Efficient Approach to Build Accurate Behavioral Models of PLL Designs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 391
EP - 398
AU - Chin-Cheng KUO
AU - Yu-Chien WANG
AU - Chien-Nan Jimmy LIU
PY - 2006
DO - 10.1093/ietfec/e89-a.2.391
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2006
AB - In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.
ER -
English
