A four-quadrant-input linear transconductor generating a product or a product sum current is proposed. The proposed circuit eliminates the influence of channel length modulation and expands a dynamic input voltage range. As an application of the proposed circuit, the four-quadrant analog multiplier is designed. The four-quadrant analog multiplier consists of the proposed circuit, an input circuit and a class AB current buffer. HSPICE simulation results with 0.35 µm n-well single CMOS process parameter are shown in order to evaluate the proposed circuit.

Linearity of a transconductor with a theoretical linear characteristic is deteriorated by mobility degradation, in practice. In this paper, a technique to improve the linearity by combining a source-coupled pair with the transconductor is proposed. The proposed transconductor is the circuit that the deteriorated linearity of the conventional part is compensated by the transconductance characteristic of the source-coupled pair. In order to confirm the validity of the proposed technique, SPICE simulation is carried out. The transconductance change ratio of the proposed technique is about 1% and is 1/10 or less of the conventional circuit.

This study presents a new current-mirror sense amplifier (CMSA) design for high-speed static random access memory (SRAM) applications. The proposed CMSA can directly sense the current of memory cell and only needs two transistor stages cascaded from V_DD to GND for achieving the low-voltage operation. Moreover, the sensing speed of the proposed CMSA is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Based on the simulation with using the TSMC 0.25-µm 2P4M CMOS process parameter, the proposed CMSA can effectively work at 500 MHz-1 GHz with working voltage as low as 1.5 V. Simulated results show that the proposed CMSA has a much speed improvement compared with the conventional sense amplifiers. Also, the effectiveness of the proposed CMSA is demonstrated with a read-cycle-only memory system to show the good performance for SRAM applications.

A false lock free delay-locked loop(DLL) achieving a wide frequency operation and a fine timing resolution is presented. A novel false lock detection technique is proposed to solve the trade-off between a wide frequency range and false locks. This technique enables a fine timing resolution even at a high frequency. In addition, the duty cycle of the input clock is not required to be 50%. This technique is applied to the DLLs in analog front-end LSIs of digital camera systems, with a range of 465 MHz (16) and a timing resolution of 9(40 stages).

In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.

In this paper by using an exactly analytic approach the clock jitter in the feedback path of the continuous time Delta Sigma modulators (CT DSM) is modeled as an additive jitter noise, providing a time invariant model for a jittery CT DSM. Then for various DAC waveforms the power spectral density (psd) of the clock jitter at the output of DAC is derived and by using an approximation the in-band power of the clock jitter at the output of the modulator is extracted. The simplicity and generality of the proposed approach are the main advantages of this paper. The MATALB and HSPICE simulation results confirm the validity of the proposed formulas.

A highly collision-resistive RFID system multiplexes communications between thousands of tags and a single reader in combination with time-domain multiplexing code division multiple access (TD-CDMA), CRC error detection, and re-transmission for error recovery. The collision probability due to a random selection of CDMA codes and TDMA channels bounds the number of IDs successfully transmitted to a reader during a limited time frame. However, theoretical analysis showed that the re-transmission greatly reduced the collision probability and that an ID error rate of 2.510^-9 could be achieved when 1,000 ID tags responded within a time frame of 400 msec in ideal communication channels. The proposed collision-resistive communication scheme for a thousand multiplexed channels was modeled on a discrete-time digital expression and an FPGA-based emulator was built to evaluate a practical ID error rate under the presence of background noise in communication channels. To achieve simple anti-noise communication in a multiple-response RFID system, as well as unurged re-transmission of ID data, adjusting of correlator thresholds provides a significant improvement to the error rate. Thus, the proposed scheme does not require a reader to request ID transmission to erroneously responding tags. A reader also can lower noise influence by using correlator thresholds, since the scheme multiplexes IDs by CDMA-based communication. The effectiveness of the re-transmission was confirmed experimentally even in noisy channels, and the ID error rate derived from the emulation was 1.910^-5. The emulation was useful for deriving an optimum set of RFID system parameters to be used in the design of mixed analog and digital integrated circuits for RFID communication.

A network for the detection of an approaching object with simple-shape recognition is proposed based on lower animal vision. The locust can detect an approaching object through a simple process in the descending contralateral movement detector (DCMD) in the locust brain, by which the approach velocity and direction of the object is determined. The frog can recognize simple shapes through a simple process in the tectum and thalamus in the frog brain. The proposed network is constructed of simple analog complementary metal oxide semiconductor (CMOS) circuits. The integrated circuit of the proposed network is fabricated with the 1.2 µm CMOS process. Measured results for the proposed circuit indicate that the approach velocity and direction of an object can be detected by the output current of the analog circuit based on the DCMD response. The shape of moving objects having simple shapes, such as circles, squares, triangles and rectangles, was recognized using the proposed frog-visual-system-based circuit.

A two-dimensional network for motion detection constructed of simple analog circuits was proposed and designed based on the frog visual system. In the frog visual system, the two-dimensional motion of a moving object can be detected by performing simple information processing in the tectum and thalamus of the frog brain. The measured results of the test chip fabricated by a 1.2 µm complementary metal oxide semiconductor (CMOS) process confirmed the correct operation of the basic circuits in the network. The results obtained with the simulation program with integrated circuit emphasis (SPICE) showed that the proposed network can detect the motion direction and velocity of a moving object. Thus, a chip for two-dimensional motion detection was realized using the proposed network.

This work proposes a new method for RLCG interconnect model-order reductions in consideration with the adjoint network. Relationships between an original MNA network and its corresponding adjoint MNA network will be explored first. It will be shown that the congruence transformation matrix used in the one-sided projection can be constructed by using the bi-orthogonal bases developed from the Lanczos-type algorithms. In particular, if the multi-port driving-point impedance of RLCG interconnect circuits is the main concern, the transfer functions and system moments of the adjoint network can be directly calculated from those of the original RLCG interconnect network by exploring symmetric properties of the MNA formulation. Therefore, the cost of constructing the congruence transformation matrix can be simplified by up to 50% of the previous methods. Comparative studies among various standard methods and the proposed methods are also investigated. Experimental results on large-scale RLCG interconnect circuits will demonstrate the accuracy and the efficiency of the proposed method.

The shape-based routing needs a routing architecture with a geometrical computation framework on it. This paper introduces a novel routing architecture, Oct-Touched Tile (OTT), with a geometrical computation method along the horizontal- and vertical-constraints. The architecture is represented by the tiles spreading over the 2-D plane. Each tile is flexible to satisfy the constraints imposed for non-overlapping and sizing request. In this framework, path finding and shape-based sizing are executed on the same architecture. In experiments, our system demonstrates the performance comparable to a commercial tool. In addition, we show potential of OTT by introducing several ideas of extensions to analog layout constraints.

A novel low-voltage low-distortion analog sampling switch is proposed in this letter. A "source tracker" techniuqe is used to distinguish the real source terminal of the sampling switch. The turn-on resistance of the sampling switch is kept exactly constant. The modified switch makes the rail-to-rail input signal swing possible for low voltage. TSMC 0.18 µm standard CMOS technology is utilized in this research. Results indicate that much lower Total Harmonic Distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of the low-voltage low-distortion switched-capacitor circuits.

In this letter, my proposals for a Floating node voltage-controlled Variable Resistor circuit (FVR) are based upon its advantages as linear and compact. The performance of the proposed circuit was confirmed by PSpice simulation. The simulation results are reported in this letter.

This paper describes a numerical design procedure of element values of RC polyphase filters with equal minima in stopband and equal ripple in passband. Determination of element values of RC polyphase filters with equal-ripple characteristic have not been solved to the best knowledge of the authors. There found a paper tackling with the problem; however, it can only give sub-optimal solutions via numerical calculation [3]. We propose a numerical element value design procedure for RC polyphase filters with equi-ripple gain in both stopband and passband by using the coefficient matching method. Some design examples are given.

This paper proposes a new approach for analog portion testing, which can meet requirements for high-speed and high-accuracy testing simultaneously with reasonable cost. The key concept of the new method is cooperation of an LSI tester and some circuitry built in a target SoC device. We will explain the operation principle of the proposed method. The proposed method can be one of the methods to overcome today's expensive production test of analog portion on SoC (System on Chip) devices which heavily depends on LSI tester capability and will become harder in near future.

The paper presents an adaptive algorithm named adaptive threshold nonlinear algorithm for use in adaptive filters in the complex-number domain (c-ATNA) in applications to digital QAM systems. Although the c-ATNA is very simple to implement, it makes adaptive filters highly robust against impulse noise and at the same time it ensures filter convergence as fast as that of the well-known LMS algorithm. Analysis is developed to derive a set of difference equations for calculating transient behavior as well as steady-state performance. Experiment with simulations and theoretical calculations for some examples of filter convergence in the presence of Contaminated Gaussian Noise demonstrates that the c-ATNA is effective in combating impulse noise. Good agreement between simulated and theoretical convergence proves the validity of the analysis.

This study presents a fast adaptive algorithm for noise estimation in non-stationary environments. To make noise estimation adapt quickly to non-stationary noise environments, a robust entropy-based voice activity detection (VAD) is thus required. It is well-known that the entropy-based measure defined in spectral domain is very insensitive to the changing level of nose. To exploit the specific nature of straight lines existing on speech-only spectrogram, the proposed spectrum entropy measurement improved from spectrum entropy proposed by Shen et al. is further presented and is named band-splitting spectrum entropy (BSE). Consequently, the proposed recursive noise estimator including BSE-based VAD can update noise power spectrum accurately even if the noise-level quickly changes.

This paper discusses the least-squares linear filtering and smoothing (fixed-point and fixed-interval) problems of discrete-time signals from observations, perturbed by additive white noise, which can be randomly delayed by one sampling time. It is assumed that the Bernoulli random variables characterizing delay measurements are correlated in consecutive time instants. The marginal distribution of each of these variables, specified by the probability of a delay in the measurement, as well as their correlation function, are known. Using an innovation approach, the filtering, fixed-point and fixed-interval smoothing recursive algorithms are obtained without requiring the state-space model generating the signal; they use only the covariance functions of the signal and the noise, the delay probabilities and the correlation function of the Bernoulli variables. The algorithms are applied to a particular transmission model with stand-by sensors for the immediate replacement of a failed unit.

This paper presents a new generative approach for generating two-dimensional signals having both a low peak factor (crest factor) and a flat power spectrum. The flat power spectrum provides zero auto-correlation, except at the zero shift. The proposed method is a generative scheme, not a search method, and produces a two-dimensional signal of size 2(2n₁+1)²(2n₂+1)² for an arbitrary pair of positive integers n₁ and n₂ without any computer search. The peak factor of the proposed signal is equal to the peak factor of a single trigonometric function.

A noise reduction technique to reduce wideband and sinusoidal noise in a noisy speech is proposed. In an actual environment, background noise includes not only wideband noise but also sinusoidal noise, such as ventilation fan and engine noise. In this paper, we propose a new noise reduction system which uses two types of adaptive line enhancers (ALE) and a noise estimation filter (NEF). First, the two ALEs are used to estimate speech components. The first ALE is used to reduce sinusoidal noise superposed on speech and wideband noise, while the second ALE is used to reduce wideband noise superposed on speech. However, since the quality of the speech enhanced by two ALEs is not good enough due to the difficulty in estimating unvoiced sound using the two ALEs, the NEF is used to improve on noise reduction capability. The NEF accurately estimates the background noise from the signal occupied by noise components, which is obtained by subtracting the speech enhanced by two ALEs from noisy speech. The enhanced speech is obtained by subtracting the estimated noise from noisy speech. Furthermore, the noise reduction system with feedback path is proposed to improve further the quality of enhanced speech.

A parallel notch filter (PNF) for eliminating a sinusoidal signal whose frequency and phase are unknown, has been proposed previously. The PNF achieves both fast convergence and high estimation accuracy when the step-size for adaptation is appropriately determined. However, there has been no discussion of how to determine the appropriate step-size. In this paper, we derive the convergence condition on the step-size, and propose an adaptive algorithm with variable step-size so that convergence of the PNF is automatically satisfied. Moreover, we present a new filtering structure of the PNF that increases the convergence speed while keeping the estimation accuracy. We also derive a variable step-size scheme for the new PNF to guarantee the convergence. Simulation results show the effectiveness of the proposed method.

In recent works [1],[4], it has been shown that the damping of a linear time invariant system relates to the so-called characteristic ratios (α_k, k=1,…, n-1) which are defined by coefficients of the denominator of the transfer function. However, the exact relations are not yet fully understood. For the purpose of exploring the issue, this paper presents the analysis of time response sensitivity to the characteristic ratio change. We begin with the sensitivity of output to the perturbations of coefficients of the system denominator and then the first order approximation of the α_k perturbation effect is computed by an explicit transfer function. The results are extended to all-pole systems in order to investigate which characteristic ratios act dominantly on step response. The same analysis is also performed to a special class of systems whose denominator is composed of so called K-polynomial. Finally, some illustrative examples are given.

In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated.

As process technologies decrease below a hundred nanometers, the variability of circuit parameters increases, and statistical timing analysis, which analyzes the distribution of the critical delay of a circuit, is receiving a great deal of attention. In such statistical approaches, correlations between random variables are important to the accuracy of analysis. Since interconnect delays dominate in recent technology, their correlations are of primary concern in statistical timing analysis. In this paper, we propose an efficient algorithm for calculating correlation coefficients between Elmore interconnect delays with the use of Gaussian distributions. Our algorithm is efficient and yields reasonable results for correlations between interconnect delays of different nets. In order to evaluate the performance of the proposed algorithm, we show experimental results compared against Monte-Carlo simulations using SPICE.

The 2-terminal shortest path problem is to find a shortest path between two specified vertices in a given graph G. In this paper, we consider this problem in the following situation: G is given before the two vertices are specified so that some preprocessing is allowed to reduce the response time. We present a method for calculating lower bounds of the length of the shortest path for any pair of vertices. Experimental results show that the A^* algorithm with our method performs much better than previous methods.

We consider a network, where a special data called certificate is issued between two users, and all certificates issued by the users in the network can be represented by a directed graph. For any two users u and v, when u needs to send a message to v securely, v's public-key is needed. The user u can obtain v's public-key using the certificates stored in u and v. We need to disperse the certificates to the users such that when a user wants to send a message to the other user securely, there are enough certificates in them to get the reliable public-key. In this paper, when a certificate graph and a set of communication requests are given, we consider the problem to disperse the certificates among the nodes in the network, such that the communication requests are satisfied and the total number of certificates stored in the nodes is minimized. We formulate this problem as MINIMUM CERTIFICATE DISPERSAL (MCD for short). We show that MCD is NP-Complete, even if its input graph is restricted to a strongly connected graph. We also present a polynomial-time 2-approximation algorithm MinPivot for strongly connected graphs, when the communication requests satisfy some restrictions. We introduce some graph classes for which MinPivot can compute optimal dispersals, such as trees, rings, and some Cartesian products of graphs.

Montgomery algorithm has demonstrated its effectiveness in applications like cryptosystems. Most of the existing works on finding the Montgomery inverse of an element over the Galois field are based on the software implementation, which is then extended to derive the scalable hardware architecture. In this work, we consider a fundamental change at the algorithmic level and eliminate the potential problems in hardware implementation which makes the resulting modified Montgomery inverse algorithm over GF(2^m) very suitable for hardware realization. Due to its structural simplicity, the modified algorithm can be easily mapped onto a high-speed and possibly low-complexity circuit. Experimental results show that our development can achieve both the area and speed advantages over the previous work when the inversion operation over GF(2^m) is under consideration and the improvement becomes more significant when we increase the value of m as in the applications of cryptosystems. The salient property of our development sustains the high-speed operation as well as low hardware complexity over a wide range of m for commercial cryptographic applications and makes it suitable for both the scalable architecture and direct hardware implementation.

Because fault-based attacks on cryptosystems have been proven effective, fault diagnosis and tolerance in cryptography have started a new surge of research and development activity in the field of applied cryptography. Without magnitude comparisons, the Montgomery multiplication algorithm is very attractive and popular for Elliptic Curve Cryptosystems. This paper will design a Montgomery multiplier array with a bit-parallel architecture in GF(2^m) with concurrent error detection capability to protect it against fault-based attacks. The robust Montgomery multiplier array with concurrent error detection requires only about 0.2% extra space overhead (if m=512 is as an example) and requires four extra clock cycles compared to the original Montgomery multiplier array without concurrent error detection.

The belief propagation (BP) algorithm is a tool with which one can calculate beliefs, marginal probabilities, of probabilistic networks without loops (e.g., Bayesian networks) in a time proportional to the number of nodes. For networks with loops, it may not converge and, even if it converges, beliefs may not be equal to exact marginal probabilities although its application is known to give remarkably good results such as in the coding theory. Tatikonda and Jordan show a theoretical result on the convergence of the algorithm for probabilistic networks with loops in terms of the theory of Markov random fields on trees and give a sufficient condition of the convergence of the algorithm. In this paper, we discuss the "impatient" update rule as well as the "lazy" update rule discussed in Tatikonda and Jordan. In the viewpoint of the theory of Markov random fields, it is shown that the rule for updating both gives essentially the same results and the impatient update rule is expected to converge faster than the lazy one. Numerical experiments are also given.

This paper presents two improved triple parity placement schemes, the HDD1 (Horizontal and Dual Diagonal) scheme and the HDD2 scheme, to enhance the reliability of a disk array system. Both the schemes can tolerate up to three column disk failures by using three types of parity information (horizontal, diagonal, and anti-diagonal parities) in a disk array. HDD1 scheme can decrease the frequency of bottlenecks because its horizontal and anti-diagonal parities are uniformly distributed over a disk array, with its diagonal parities placed in dedicated column disks. HDD2 scheme possesses one more column disks than HDD1 to store the horizontal parities and an additional diagonal parity; its anti-diagonal and diagonal parities are placed in the same way as in HDD1 scheme, only with a minor difference. The encoding and decoding algorithms of the two schemes are rather simple and straightforward, some steps of its procedure can even be executed in parallel, which makes the disk failure recovery faster.

This paper proposes a parity placement scheme, Row-Oblique Parity (ROP), for protecting against double disk failure in disk array systems. It stores all data unencoded, and uses only exclusive-or (XOR) operations to compute parity. ROP is provably optimal in computational complexity, both during construction and reconstruction. It is optimal in the capacity of redundant information stored and accessed. The simplicity of ROP allowed us to implement it within the current available RAID framework.

This paper presents a simple, yet effective hybrid of the minimum mean square error (MMSE) multi-user detection (MUD) and successive interference cancellation (SIC) for direct-sequence code division multiple access (DS-CDMA) systems. The proposed hybrid MUD first divides the users into groups, with each group consisting of users with a close power level. The SIC is then used to distinguish users among different groups, while the MMSE MUD is used to detect signals within each group. To further improve the performance impaired by the propagation errors, an information reuse scheme is also addressed, which can be used in conjunction with the hybrid MMSE/SIC MUD to adequately cancel the multiple access interferences (MAIs) so as to attain more accurate detections. Furthermore, the asymptotic multiuser efficiency (AME), a measure to characterize the near-far resistance capability, is also conducted to provide further insights into the new detectors. Furnished simulations, in both additive white Gaussian noise (AWGN) channels and slow flat Rayleigh fading channels, show that the performances of the proposed hybrid MMSE/SIC detectors, with or without the decision aided scheme, are superior to that of the SIC and, especially, the one with decision aided is close to that of the MMSE MUD but with substantially lower computational complexity.

This letter proposes a new asymmetric watermarking scheme. In the proposed scheme, a non-full rank matrix is applied to an embedded watermark to form an asymmetric detection watermark. To detect the embedded watermark, the watermarked signal is transformed through the matrix firstly. Then a correlation test between the detection watermark and the transformed signal is performed. This scheme allows for the public release of all information, except for the embedded watermark. The performance of the scheme is analyzed, and the simulation results demonstrate that the proposed scheme is secure and robust to some common attacks.

R-regular Mth band filters are an important class of digital filters and are used in constructing Mth-band wavelet filter banks, where the regularity is essential. But this kind of filter has larger stopband peak errors compared with a minimax filter of the same length. In this paper, peak errors in stopband of R-regular 4th-band filters are reduced by means of superimposing two filters with successive regularities. Then the stopband peak errors in the resulting filters are compared with the original ones. The results show that the stopband peak errors are reduced significantly in the synthesized filter that has the same length as the longer one of the two original filters, at the cost of regularity.

The Visual Secret Sharing (VSS) scheme proposed by Naor and Shamir is a perfectly secure scheme to share a secret image. By using m sub pixels to represent one pixel, we encrypt the secret image into several noise-like shadow images. The value of m is known as the pixel expansion. More pixel expansion increases the shadow size and makes VSS schemes impractical for real application. In this paper, we propose new size-reduced VSS schemes and dramatically decrease the pixel expansion by a half.

In RSA public-key cryptosystem, a small private key is often preferred for efficiency but such a small key could degrade security. Thus the Chinese Remainder Theorem (CRT) is tactically used, especially in time-critical applications like smart cards. As for using the CRT in RSA, care must be taken to resist partial key exposure attacks. While it is common to choose two distinct primes with similar size in RSA, May has shown that a composite modulus N can be factored in the balanced RSA with the CRT of half of the least (or most) significant bits of a private key is revealed with a small public key. However, in the case that efficiency is more critical than security, such as smart cards, unbalanced primes might be chosen. Thus, we are interested in partial key exposure attacks to the unbalanced RSA with the CRT. In this paper, we obtain the similar results as the balanced RSA. We show that in the unbalanced RSA if the N^1/4 least (or most) significant bits are revealed, a private key can be recovered in polynomial time under a small public key.

In this letter, we propose a butterfly structure for rate 2/n convolutional codes to reduce the computational complexity of Viterbi decoders. By using the butterfly structure, the branch metric computation complexity of some best known codes can be reduced by a factor of 2 or 4.

The present paper introduces an improved construction of a class of binary sequences having a zero-correlation zone (hereafter binary ZCZ sequence set). The cross-correlation function and the side-lobe of the auto-correlation function of the proposed sequence set is zero for the phase shifts within the zero-correlation zone. The present paper shows that such a construction generates a binary ZCZ sequence set from an arbitrary M-sequence. The previously reported sequence construction of binary ZCZ sequence sets from an M-sequence can generate a single series of binary ZCZ sequence sets from an M-sequence. The present paper proposes an improved sequence construction that can generate more than one series of binary ZCZ sequence sets from an M-sequence.

This paper introduces a method of merging systolic messy arrays. A systolic messy array features data-triggered PEs placed in various directions in a 2-dimensional lattice plane. The two kinds of merging are described as Shared-array and Interlacing-array. A shared-array is a systolic messy array where at least two systolic messy arrays share portions of their arrays and the data on the portions is shared with all systolic messy arrays. An interlacing-array is a systolic messy array where at least two systolic messy arrays share portions of their arrays but where the data on the portions is not shared. The data on the portions flows independently so that an interlacing-array can deal with each of its own calculations without interference. Several examples of the two kinds of merging are presented and their construction methods are illustrated.