This paper describes an ultra low power, motion estimation (ME) processor for MPEG2 HDTV resolution video. It adopts a Gradient Descent Search (GDS) algorithm that drastically reduces required computational power to 6 GOPS. A SIMD datapath architecture optimized for the GDS algorithm decreases the clock frequency and operating voltage. A low power 3-port SRAM with a write-disturb-free cell array arrangement is newly designed for image data caches of the processor. The proposed ME processor contains 7-M transistors, integrated in 4.50 mm 3.35 mm area using 0.13 µm CMOS technology. Estimated power consumption is less than 100 mW at 81 MHz@1.0 V. The processor is applicable to a portable HDTV system.

Asymmetric slope differential CMOS (ASD-CMOS) and asymmetric slope differential dynamic logic (ASDDL) surpass the highest speed that conventional CMOS logic circuits can achieve, resulting from deeply shortened rise time along with relatively prolonged fall time. ASD-CMOS is a static logic and ASDDL is a dynamic logic without per-gate synchronous clock signal, each of which needs two-phase operation as well as differential signaling, however, interleaved precharging hides the prolonged fall time and BDD-based compound logic design mitigates area increase. ASD-CMOS 16-bit multiplier in a 0.18-µm CMOS technology demonstrates 1.78 nsec per an operation, which reaches 34% reduction of the best delay time achieved by a multiplier using a CMOS standard cell library that is conventional yet tuned to the optimum in energy-delay products. ASDDL can be superior to DCVS-DOMINO circuits not only in delay time but also in area and even in power. ASDDL 16-bit multiplier achieves delay and power reduction of 4% and 20%, respectively, compared with DCVS-DOMINO realization. A prototype ASD-CMOS 16-bit multiplier with built-in test circuitry fabricated in a 0.13-µm CMOS technology operates with the delay time of 1.57 nsec at 1.2 V.

A highly collision-resistive RFID system multiplexes communications between thousands of tags and a single reader in combination with time-domain multiplexing code division multiple access (TD-CDMA), CRC error detection, and re-transmission for error recovery. The collision probability due to a random selection of CDMA codes and TDMA channels bounds the number of IDs successfully transmitted to a reader during a limited time frame. However, theoretical analysis showed that the re-transmission greatly reduced the collision probability and that an ID error rate of 2.510-9 could be achieved when 1,000 ID tags responded within a time frame of 400 msec in ideal communication channels. The proposed collision-resistive communication scheme for a thousand multiplexed channels was modeled on a discrete-time digital expression and an FPGA-based emulator was built to evaluate a practical ID error rate under the presence of background noise in communication channels. To achieve simple anti-noise communication in a multiple-response RFID system, as well as unurged re-transmission of ID data, adjusting of correlator thresholds provides a significant improvement to the error rate. Thus, the proposed scheme does not require a reader to request ID transmission to erroneously responding tags. A reader also can lower noise influence by using correlator thresholds, since the scheme multiplexes IDs by CDMA-based communication. The effectiveness of the re-transmission was confirmed experimentally even in noisy channels, and the ID error rate derived from the emulation was 1.910-5. The emulation was useful for deriving an optimum set of RFID system parameters to be used in the design of mixed analog and digital integrated circuits for RFID communication.

Asymmetric Slope Dual Mode Differential Logic (ASDMDL) embodies high-speed dynamic and low-power static operations in a single design. Two-phase dual-rail logic signaling is used in a high-speed operation, where a logical evaluation is preceded by pre-charge, and it asserts one of the rails with an asymmetrically shortened rise transition to express a binary result. On the other hand, single-phase differential logic signaling eliminates pre-charge and leads to a low-power static operation. The operation mode is defined by the logic signaling styles, and no control signal is needed in the logic cell. The design of mixed CMOS and ASDMDL logic circuits can be automated with general logic synthesis and place-and-route techniques, since the physical ASDMDL cell is prepared in such a way to comply with a CMOS standard-cell design flow. A mixed ASDMDL/CMOS micro-processor in a 0.18-µm CMOS technology demonstrated 232 MHz operation, corresponding to 14% speed improvement over a full CMOS implementation. This was achieved by substituting ASDMDL cells for only 4% of the CMOS logic cells in data paths. The low-speed operation of ASDMDL at 100 MHz was nearly equivalent to that of CMOS. However, power consumption was reduced by 3% due to the use of ASDMDL complex logic cells. Area overhead was less than 4%.

A highly collision-resistive RFID system multiplexes communications between thousands of transponders and a single reader using TH-CDMA based anti-collision scheme. This paper focuses on the back-end design consideration of such an RFID system with the deployment of high-level modeling techniques, accompanying a technical comparison of physical-level description, hardware-based emulation, and software-based simulation. A new rapid-prototyping simulation system was constructed to evaluate the robustness of a multiplexed RFID link system with more than 1,000 channels in the presence of field disturbances, and the design parameters of the back-end digital signal processing that dominated anti-collision performance were explored. Finally, the derived optimum parameters were applied to the design of a back-end digital integrated circuit to be installed in collision-resistive transponder circuitry.

This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The technique utilizes a commercially available logic synthesis tool that has been well established for static CMOS logic design, where an intermediate library is devised for logic synthesis likely as static CMOS, and then a resulting synthesized circuit is translated automatically into ASDDL implementation at the gate-level logic schematic level as well as at the physical-layout level. A design example of an ASDDL 16-bit multiplier synthesized in a 0.18-µm CMOS technology shows an operation delay time of 1.82 nsec, which is a 32% improvement over a static CMOS design with a static logic standard-cell library that is finely tuned for energy-delay products. Design with the 16-bit multiplier led to a design time for an ASDDL based dynamic digital circuit 300 times shorter than that using a fully handcrafted design, and comparable with a static CMOS design.

An integrated multi-level simulation environment is developed for a highly collision-resistant RFID system. An analog/mixed-signal (AMS) simulator for a circuit-level description of analog front-end power/signal transmission through electro-magnetic coupling is concurrently connected to a tailored software simulator for system-level description of digital back-end processing of TH-CDMA based anti-collision communication. The feasibility of the RFID system in which more than 1,000 transponders can be identified by a single reader in 400 msec is successfuly explored, under a practical presence of field disturbances such as background noises in communication channels as well as variations of electro-magnetic coupling strengths for power transmission.