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[Author] Yoshinori TANAKA(10hit)

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  • Normalized Least Mean EE' Algorithm and Its Convergence Condition

    Kensaku FUJII  Mitsuji MUNEYASU  Takao HINAMOTO  Yoshinori TANAKA  

     
    PAPER

      Vol:
    E84-A No:4
      Page(s):
    984-990

    The normalized least mean square (NLMS) algorithm has the drawback that the convergence speed of adaptive filter coefficients decreases when the reference signal has high auto-correlation. A technique to improve the convergence speed is to apply the decorrelated reference signal to the calculation of the gradient defined in the NLMS algorithm. So far, only the effect of the improvement is experimentally examined. The convergence property of the adaptive algorithm to which the technique is applied is not analized yet enough. This paper first defines a cost function properly representing the criterion to estimate the coefficients of adaptive filter. The name given in this paper to the adaptive algorithm exploiting the decorrelated reference signal, 'normalized least mean EE' algorithm, exactly expresses the criterion. This adaptive algorithm estimates the coefficients so as to minimize the product of E and E' that are the differences between the responses of the unknown system and the adaptive filter to the original and the decorrelated reference signals, respectively. By using the cost function, this paper second specifies the convergence condition of the normalized least mean EE' algorithm and finally presents computer simulations, which are calculated using real speech signal, to demonstrate the validity of the convergence condition.

  • Analysis on the Convergence Property of Quantized-x NLMS Algorithm

    Kensaku FUJII  Yoshinori TANAKA  

     
    PAPER-Adaptive Signal Processing

      Vol:
    E84-A No:8
      Page(s):
    1840-1847

    The adaptive system design by 16-bit fixed point processing enables to employ an inexpensive digital signal processor (DSP). The narrow dynamic range of such 16 bits, however, does not guarantee the same performance that is confirmed beforehand by computer simulations. A cause of degrading the performance originates in the operation halving the word length doubled by multiplication. This operation rounds off small signals staying in the lower half of the doubled word length to zero. This problem can be solved by limiting the multiplier to only its sign () like the signed regressor algorithm, named 'bi-quantized-x' algorithm in this paper, for the convenience mentioned below. This paper first derives the equation describing the convergence property provided by a type of signed regressor algorithms, the bi-quantized-x normalized least mean square (NLMS) algorithm, and then formulates its convergence condition and the step size maximizing the convergence rate. This paper second presents a technique to improve the convergence property. The bi-qiantized-x NLMS algorithm quantizes the reference signal to 1 according to the sign of the reference signal, whereas the technique moreover assigns zero to the reference signal whose amplitude is less than a predetermined level. This paper explains the principle that the 'tri-qunatized-x' NLMS algorithm employing the technique can improve the convergence property, and confirms the improvement effect by computer simulations.

  • Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition

    Masao MORIMOTO  Yoshinori TANAKA  Makoto NAGATA  Kazuo TAKI  

     
    PAPER-Logic Synthesis

      Vol:
    E88-A No:12
      Page(s):
    3324-3331

    This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The technique utilizes a commercially available logic synthesis tool that has been well established for static CMOS logic design, where an intermediate library is devised for logic synthesis likely as static CMOS, and then a resulting synthesized circuit is translated automatically into ASDDL implementation at the gate-level logic schematic level as well as at the physical-layout level. A design example of an ASDDL 16-bit multiplier synthesized in a 0.18-µm CMOS technology shows an operation delay time of 1.82 nsec, which is a 32% improvement over a static CMOS design with a static logic standard-cell library that is finely tuned for energy-delay products. Design with the 16-bit multiplier led to a design time for an ASDDL based dynamic digital circuit 300 times shorter than that using a fully handcrafted design, and comparable with a static CMOS design.

  • Interference Reduction Scheme for UHF Passive RFID Systems Using Modulation Index Control

    Yoshinori TANAKA  Iwao SASASE  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E92-B No:4
      Page(s):
    1272-1281

    The performance of a UHF-band passive RFID system in a dense multi-reader environment is limited by both the reader-to-reader interference and reader-to-tag interference. In this paper, first, we propose a combination of subcarrier modulation backscattering and reduced carrier frequency offset among readers to reduce both the reader-to-reader interference and the reader-to-tag interference. Then, we propose a new distributed modulation index control scheme using the readers' estimation of the tag's SINR in order to further reduce the reader-to-tag interference. By adaptively controlling each reader's transmission modulation index, the asymmetric reader-to-tag interference can be effectively controlled to satisfy the required SINR of tags. Computer simulations show that the proposed scheme can reduce the minimum required inter-reader distance or increase the number of concurrently operable readers in dense multi-reader environments, especially when there are large differences in the levels of reader-to-tag interference. We show some optimizations of the proposed scheme for practical RFID applications. We also propose a bandwidth efficient modulation scheme for reader transmission which is suitable for the proposed modulation index control scheme.

  • Response Time Improvement of OCB Mode TFT-LCDs by Using Capacitively Coupled Driving Method

    Kenji NAKAO  Shoichi ISHIHARA  Yoshinori TANAKA  Daiichi SUZUKI  Ichirou SATOU  Tsuyoshi UEMURA  Keisuke TSUDA  Noriyuki KIZU  Junichi KOBAYASHI  

     
    PAPER-Active Matrix Displays

      Vol:
    E84-C No:11
      Page(s):
    1624-1629

    We have developed a super-fast response OCB (Optically self-Compensated Birefringence) mode TFT-LCD by using capacitively coupled driving method (CC driving method). Response time with this driving method has been improved by the twice or more compared with that of a conventionally driven TFT-LCD. Even at a low temperature, 0 degree, this panel can response within one field time, 16.7 ms, between every gray scale levels. We developed a prototype OCB mode LCD with newly designed compensation films, that achieved a wide viewing angle characteristic of 160 degrees horizontally and 140 degrees vertically under the condition of that the contrast ratio exceeds 10:1.

  • Convergence Property of Tri-Quantized-x NLMS Algorithm

    Kensaku FUJII  Yoshinori TANAKA  

     
    LETTER-Digital Signal Processing

      Vol:
    E83-A No:12
      Page(s):
    2739-2742

    The signed regressor algorithm, a variation of the least mean square (LMS) algorithm, is characterized by the estimation way of using the clipped reference signals, namely, its sign (). This clipping, equivalent to quantizing the reference signal to 1, only increases the estimation error by about 2 dB. This paper proposes to increase the number of the quantization steps to three, namely, 1 and 0, and shows that the 'tri-quantized-x' normalized least mean square (NLMS) algorithm with three quantization steps improves the convergence property.

  • RAN Slicing with Inter-Cell Interference Control and Link Adaptation for Reliable Wireless Communications Open Access

    Yoshinori TANAKA  Takashi DATEKI  

     
    PAPER-Terrestrial Wireless Communication/Broadcasting Technologies

      Vol:
    E107-B No:7
      Page(s):
    513-528

    Efficient multiplexing of ultra-reliable and low-latency communications (URLLC) and enhanced mobile broadband (eMBB) traffic, as well as ensuring the various reliability requirements of these traffic types in 5G wireless communications, is becoming increasingly important, particularly for vertical services. Interference management techniques, such as coordinated inter-cell scheduling, can enhance reliability in dense cell deployments. However, tight inter-cell coordination necessitates frequent information exchange between cells, which limits implementation. This paper introduces a novel RAN slicing framework based on centralized frequency-domain interference control per slice and link adaptation optimized for URLLC. The proposed framework does not require tight inter-cell coordination but can fulfill the requirements of both the decoding error probability and the delay violation probability of each packet flow. These controls are based on a power-law estimation of the lower tail distribution of a measured data set with a smaller number of discrete samples. As design guidelines, we derived a theoretical minimum radio resource size of a slice to guarantee the delay violation probability requirement. Simulation results demonstrate that the proposed RAN slicing framework can achieve the reliability targets of the URLLC slice while improving the spectrum efficiency of the eMBB slice in a well-balanced manner compared to other evaluated benchmarks.

  • Analysis on the Convergence Property of the Sub-RLS Algorithm

    Kensaku FUJII  Mitsuji MUNEYASU  Takao HINAMOTO  Yoshinori TANAKA  

     
    LETTER-Digital Signal Processing

      Vol:
    E84-A No:10
      Page(s):
    2591-2594

    The sub-recursive least squares (sub-RLS) algorithm estimates the coefficients of adaptive filter under the least squares (LS) criterion, however, does not require the calculation of inverse matrix. The sub-RLS algorithm, based on the different principle from the RLS algorithm, still provides a convergence property similar to that of the RLS algorithm. This paper first rewrites the convergence condition of the sub-RLS algorithm, and then proves that the convergence property of the sub-RLS algorithm successively approximates that of the RLS algorithm on the convergence condition.

  • An Improved Sliding Window Algorithm for Max-Log-MAP Turbo Decoder and Its Programmable LSI Implementation

    Hirohisa GAMBE  Yoshinori TANAKA  Kazuhisa OHBUCHI  Teruo ISHIHARA  Jifeng LI  

     
    PAPER-Electronic Circuits

      Vol:
    E88-C No:3
      Page(s):
    403-412

    Thanks to the possibility of being able to implement them in decoders in relatively simple ways, turbo codes are being applied to various areas of engineering. Wireless communications is one of the most important applications, where various types of data communications are required and the speed of information and data capacity need to be changed with different rates of parity bit puncturing being adopted to obtain highly efficient transmission. In such applications, adaptation to various turbo-coding specifications on a real-time basis is needed as well as good bit-error-rate performance. We present a new concept for simplifying metric computation and programmable circuit configurations that focuses on the convolutional decoder, which occupies a significant portion of allocated hardware, and we fundamentally treat a simplified log-domain version of the maximum a posteriori (MAP) algorithm, usually know as the Max-Log-MAP (MLM), as a base algorithm. The sliding window method provides an attractive way of computing metric values for the Max-Log-MAP. However, this algorithm does cause degradation, especially when a high rate code is used, generated by bit puncturing. We propose a new means of avoiding this problem and demonstrate that the sliding window, and a modified version as well as other methods, should be flexibly selected to utilize hardware resources depending on turbo specifications. We demonstrated that our proposed methods provide almost the same BER performance as MLM even when a high rate puncturing rate of 5/6 is applied. Finally, we describe the new hardware architecture that we invented to cope with these programmability issues. We show that a turbo-decoding circuit can be implemented in the processor core and its associated unit to configure an LSI macro circuit. The proposed unit has about 60-K gates. We demonstrate that this architecture can be applied to about the 1.5-Mbps information bit throughput of turbo decoding with a 200-MHz clock cycle, which is achievable with today's advanced CMOS technologies.

  • Interference Avoidance Algorithms for Passive RFID Systems Using Contention-Based Transmit Abortion

    Yoshinori TANAKA  Iwao SASASE  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E90-B No:11
      Page(s):
    3170-3180

    The performance of a passive RFID system in a dense multi-reader environment is limited by both reader-to-reader interference and reader-to-tag interference. In this paper, we formulate a practical RFID system model which takes into account the non-linear demodulation of the tags and the transmission spectrum of the readers. Using this model, we derive a novel linear programming formulation to obtain the optimum communication probability of the readers for a given reader deployment scenario. We then propose two novel distributed interference avoidance algorithms based on the detect-and-abort principle for multi-channel readers which can effectively mitigate the reader-to-tag interference as well as the reader-to-reader interference. Computer simulations show that the proposed algorithms can improve the successful communication probability and fairness among readers in dense reader environments, compared with the conventional listen-before-talk algorithm.