IEICE TRANSACTIONS on Fundamentals
New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications
Summary :
This study presents a new current-mirror sense amplifier (CMSA) design for high-speed static random access memory (SRAM) applications. The proposed CMSA can directly sense the current of memory cell and only needs two transistor stages cascaded from VDD to GND for achieving the low-voltage operation. Moreover, the sensing speed of the proposed CMSA is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Based on the simulation with using the TSMC 0.25-µm 2P4M CMOS process parameter, the proposed CMSA can effectively work at 500 MHz-1 GHz with working voltage as low as 1.5 V. Simulated results show that the proposed CMSA has a much speed improvement compared with the conventional sense amplifiers. Also, the effectiveness of the proposed CMSA is demonstrated with a read-cycle-only memory system to show the good performance for SRAM applications.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.2 pp.377-384
- Publication Date
- 2006/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.2.377
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
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Chun-Lung HSU, Mean-Hom HO, Chin-Feng LIN, "New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 2, pp. 377-384, February 2006, doi: 10.1093/ietfec/e89-a.2.377.
Abstract: This study presents a new current-mirror sense amplifier (CMSA) design for high-speed static random access memory (SRAM) applications. The proposed CMSA can directly sense the current of memory cell and only needs two transistor stages cascaded from VDD to GND for achieving the low-voltage operation. Moreover, the sensing speed of the proposed CMSA is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Based on the simulation with using the TSMC 0.25-µm 2P4M CMOS process parameter, the proposed CMSA can effectively work at 500 MHz-1 GHz with working voltage as low as 1.5 V. Simulated results show that the proposed CMSA has a much speed improvement compared with the conventional sense amplifiers. Also, the effectiveness of the proposed CMSA is demonstrated with a read-cycle-only memory system to show the good performance for SRAM applications.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.2.377/_p
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@ARTICLE{e89-a_2_377,
author={Chun-Lung HSU, Mean-Hom HO, Chin-Feng LIN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications},
year={2006},
volume={E89-A},
number={2},
pages={377-384},
abstract={This study presents a new current-mirror sense amplifier (CMSA) design for high-speed static random access memory (SRAM) applications. The proposed CMSA can directly sense the current of memory cell and only needs two transistor stages cascaded from VDD to GND for achieving the low-voltage operation. Moreover, the sensing speed of the proposed CMSA is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Based on the simulation with using the TSMC 0.25-µm 2P4M CMOS process parameter, the proposed CMSA can effectively work at 500 MHz-1 GHz with working voltage as low as 1.5 V. Simulated results show that the proposed CMSA has a much speed improvement compared with the conventional sense amplifiers. Also, the effectiveness of the proposed CMSA is demonstrated with a read-cycle-only memory system to show the good performance for SRAM applications.},
keywords={},
doi={10.1093/ietfec/e89-a.2.377},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 377
EP - 384
AU - Chun-Lung HSU
AU - Mean-Hom HO
AU - Chin-Feng LIN
PY - 2006
DO - 10.1093/ietfec/e89-a.2.377
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2006
AB - This study presents a new current-mirror sense amplifier (CMSA) design for high-speed static random access memory (SRAM) applications. The proposed CMSA can directly sense the current of memory cell and only needs two transistor stages cascaded from VDD to GND for achieving the low-voltage operation. Moreover, the sensing speed of the proposed CMSA is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Based on the simulation with using the TSMC 0.25-µm 2P4M CMOS process parameter, the proposed CMSA can effectively work at 500 MHz-1 GHz with working voltage as low as 1.5 V. Simulated results show that the proposed CMSA has a much speed improvement compared with the conventional sense amplifiers. Also, the effectiveness of the proposed CMSA is demonstrated with a read-cycle-only memory system to show the good performance for SRAM applications.
ER -
English
