IEICE TRANSACTIONS on Fundamentals
An Enhanced BSA for Floorplanning
Summary :
In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.2 pp.528-534
- Publication Date
- 2006/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.2.528
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
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Jyh Perng FANG, Yang-Shan TONG, Sao Jie CHEN, "An Enhanced BSA for Floorplanning" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 2, pp. 528-534, February 2006, doi: 10.1093/ietfec/e89-a.2.528.
Abstract: In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.2.528/_p
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@ARTICLE{e89-a_2_528,
author={Jyh Perng FANG, Yang-Shan TONG, Sao Jie CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Enhanced BSA for Floorplanning},
year={2006},
volume={E89-A},
number={2},
pages={528-534},
abstract={In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated.},
keywords={},
doi={10.1093/ietfec/e89-a.2.528},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - An Enhanced BSA for Floorplanning
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 528
EP - 534
AU - Jyh Perng FANG
AU - Yang-Shan TONG
AU - Sao Jie CHEN
PY - 2006
DO - 10.1093/ietfec/e89-a.2.528
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2006
AB - In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated.
ER -
English
