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An Enhanced BSA for Floorplanning

Jyh Perng FANG, Yang-Shan TONG, Sao Jie CHEN

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Summary :

In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.2 pp.528-534
Publication Date
2006/02/01
Publicized
Online ISSN
1745-1337
DOI
10.1093/ietfec/e89-a.2.528
Type of Manuscript
PAPER
Category
VLSI Design Technology and CAD

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