A four-quadrant-input linear transconductor generating a product or a product sum current is proposed. The proposed circuit eliminates the influence of channel length modulation and expands a dynamic input voltage range. As an application of the proposed circuit, the four-quadrant analog multiplier is designed. The four-quadrant analog multiplier consists of the proposed circuit, an input circuit and a class AB current buffer. HSPICE simulation results with 0.35 µm n-well single CMOS process parameter are shown in order to evaluate the proposed circuit.
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Masakazu MIZOKAMI, Kawori TAKAKUBO, Hajime TAKAKUBO, "Four-Quadrant-Input Linear Transconductor Employing Source and Sink Currents Pair for Analog Multiplier" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 2, pp. 362-368, February 2006, doi: 10.1093/ietfec/e89-a.2.362.
Abstract: A four-quadrant-input linear transconductor generating a product or a product sum current is proposed. The proposed circuit eliminates the influence of channel length modulation and expands a dynamic input voltage range. As an application of the proposed circuit, the four-quadrant analog multiplier is designed. The four-quadrant analog multiplier consists of the proposed circuit, an input circuit and a class AB current buffer. HSPICE simulation results with 0.35 µm n-well single CMOS process parameter are shown in order to evaluate the proposed circuit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.2.362/_p
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@ARTICLE{e89-a_2_362,
author={Masakazu MIZOKAMI, Kawori TAKAKUBO, Hajime TAKAKUBO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Four-Quadrant-Input Linear Transconductor Employing Source and Sink Currents Pair for Analog Multiplier},
year={2006},
volume={E89-A},
number={2},
pages={362-368},
abstract={A four-quadrant-input linear transconductor generating a product or a product sum current is proposed. The proposed circuit eliminates the influence of channel length modulation and expands a dynamic input voltage range. As an application of the proposed circuit, the four-quadrant analog multiplier is designed. The four-quadrant analog multiplier consists of the proposed circuit, an input circuit and a class AB current buffer. HSPICE simulation results with 0.35 µm n-well single CMOS process parameter are shown in order to evaluate the proposed circuit.},
keywords={},
doi={10.1093/ietfec/e89-a.2.362},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - Four-Quadrant-Input Linear Transconductor Employing Source and Sink Currents Pair for Analog Multiplier
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 362
EP - 368
AU - Masakazu MIZOKAMI
AU - Kawori TAKAKUBO
AU - Hajime TAKAKUBO
PY - 2006
DO - 10.1093/ietfec/e89-a.2.362
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2006
AB - A four-quadrant-input linear transconductor generating a product or a product sum current is proposed. The proposed circuit eliminates the influence of channel length modulation and expands a dynamic input voltage range. As an application of the proposed circuit, the four-quadrant analog multiplier is designed. The four-quadrant analog multiplier consists of the proposed circuit, an input circuit and a class AB current buffer. HSPICE simulation results with 0.35 µm n-well single CMOS process parameter are shown in order to evaluate the proposed circuit.
ER -