A technique that enables a SSCG to fine-tune an output signal frequency and a spread ratio is presented. Proposed SSCG achieves the output signal frequency from 1.2 GHz to 3.0 GHz and the spread ratio from 0 to 30000 ppm. The fine-tuning technique achieves 30 ppm adjustment of the output signal frequency and 200 ppm adjustment of the spread ratio. This technique is achieved by controlling a triangular modulation signal characteristics generated by a proposed digital controlled wave generator. A proposed multi-modulus divider can have a divide ratio of 4/5 and 8/9. This SSCG has been fabricated in a 0.13-µm CMOS process. The output signal frequency-range and the spread ratio are achieved fluently from 0.1 to 3.0 GHz and from 0 to 30000 ppm, respectively. EMI noise is suppressed at less than 17.1 dB at the output signal frequency of 3.0 GHz and spread ratio of 30000 ppm.

We have developed a spread-spectrum Phase-Locked Loop (PLL) for serial Advanced Technology Attachment (ATA) applications. We investigated the relation between the output jitter of PLLs in serial ATA applications and ΣΔ modulators in PLLs. On the basis of this study, we developed a spread-spectrum PLL for serial ATA applications and achieved a combination of small jitter and large electromagnetic interference (EMI) peak power reduction. This was achieved using two key components: multi-bit ΣΔ-controlled PLL and voltage-controlled oscillation with cross-coupled load delay cells. Using a 0.15-µm complementary metal-oxide semiconductor process, we fabricated a complete serial ATA transceiver featuring a spread-spectrum clock generator (SSCG). We achieved a spread-spectrum PLL with 10-dB EMI reduction and 8.1 ps random jitter for use in serial ATA applications. All other measured results for SSCG performance were very good and showed that the spread-spectrum generator more than satisfies serial ATA specifications.

A serial ATA PHY fabricated in a 0.15-µm CMOS process performs the serial ATA operation in an asynchronous transition by using large variation in the reference clock. This technique calibrates a transmission signal frequency by utilizing the received signal. This is achieved by calibrating the divide ratio of a spread-spectrum clock generator (SSCG). This technique enables a serial ATA PHY to use reference oscillators with a production-frequency tolerance of less than 400ppm, i.e., higher than the permissible TX frequency variations (i.e., 350ppm). The calibrated transmission signal achieved a total jitter of 3.9ps.