Novel deterministic digital calibration of pipelined ADC has been proposed and analyzed theoretically. Each MDAC is dithered exploiting its inherent redundancy during the calibration. The dither enables fast accurate convergence of calibration without requiring any accurate reference signal and hence with minimum area and power overhead. The proposed calibration can be applied to both the 1.5-bit/stage MDAC and the multi-bit/stage MDAC. Due to its simple structure and algorithm, it can be modified to the background calibration easily. The effectiveness of the proposed calibration has been confirmed by both the extensive simulations and the measurement of the prototype 0.13-µm-CMOS 50-MS/s pipelined ADC using the op-amps with only 37-dB gain. As expected, SNDR and SFDR have improved from 35.5dB to 58.1dB and from 37.4dB to 70.4dB, respectively by the proposed calibration.

An entire dual-mode transceiver capable of both the conventional GFSK-modulated Bluetooth and the Medium-Rate π/4-DQPSK-modulated Bluetooth has been investigated and reported. The transmitter introduces a novel two-point-modulated polar-loop technique without the global feedback to realize reduced power consumption, small chip area and also high modulation accuracy. The receiver shares all the circuits for both operating modes except the demodulators and also features a newly-proposed cancellation technique of the carrier-frequency offset. The transceiver has been confirmed by system or circuit simulations to meet all the dual-mode Bluetooth specifications. The simulation results show that the transmitting power can be larger than 10 dBm while achieving the total power efficiency above 30% and also RMS DEVM of 0.050. It was also confirmed by simulation that the receiver is expected to attain the sensitivity of -85 dBm in both modes while satisfying the image-rejection and the blocker-suppression specifications. The proposed transceiver will provide a low-cost, low-power single-chip RF-IC solution for the next-generation Bluetooth communication.

We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3 3 mm2; this very small area was realized by the advantages of the proposed transceiver architecture. The transceiver also achieved good minimum input sensitivity of -85 dBm and showed interference performance that satisfied the requirements of the Bluetooth standard.

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, Δ Vt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5 V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for ΔVt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5 V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

3D ultrasound imagers require low-noise amplifier (LNA) with much lower power consumption and smaller chip area than conventional 2D imagers because of the huge amount of transducer channels. This paper presents a low-power small-size LNA with a novel current-reuse circuitry for 3D ultrasound imaging systems. The proposed LNA is composed of a differential common source amplifier and a source-follower driver which share the current without using inductors. The LNA was fabricated in a 0.18-μm CMOS process with only 0.0056mm2. The measured results show a gain of 21dB and a bandwidth of 9MHz. The proposed LNA achieves an average noise density of 11.3nV/√Hz, and the 2nd harmonic distortion below -40dBc with 0.1-Vpp input. The supply current is 85μA with a 1.8-V power supply, which is competitive with conventional LNAs by finer CMOS process.

The use of a two-point modulator with variable PLL loop bandwidth as a GFSK signal generator is proposed. Delta-sigma modulation is adopted for the modulator. Through the combination of a variable PLL feedback loop and delta-sigma modulation, both a fast settling time and very clear eye opening are achieved for the modulator. We fabricate it in 0.35-µm BiCMOS process technology. The two-point modulator has a center-frequency drift of only 14.9 kHz, much lower than the 178-kHz result for a single time slot in the case of direct VCO modulation. This is due to the PLL feedback loop. Evaluation also confirmed that the circuit satisfies the various characteristics required of a Bluetooth transmitter. The two-point modulator is also applicable to other transceivers which use FSK or PSK modulation, i.e. forms of modulation where a constant signal level is transmitted, and thus contributes to the simplification of a range of wireless transmitters.

We have developed a spread-spectrum Phase-Locked Loop (PLL) for serial Advanced Technology Attachment (ATA) applications. We investigated the relation between the output jitter of PLLs in serial ATA applications and ΣΔ modulators in PLLs. On the basis of this study, we developed a spread-spectrum PLL for serial ATA applications and achieved a combination of small jitter and large electromagnetic interference (EMI) peak power reduction. This was achieved using two key components: multi-bit ΣΔ-controlled PLL and voltage-controlled oscillation with cross-coupled load delay cells. Using a 0.15-µm complementary metal-oxide semiconductor process, we fabricated a complete serial ATA transceiver featuring a spread-spectrum clock generator (SSCG). We achieved a spread-spectrum PLL with 10-dB EMI reduction and 8.1 ps random jitter for use in serial ATA applications. All other measured results for SSCG performance were very good and showed that the spread-spectrum generator more than satisfies serial ATA specifications.