This paper describes a 270-MHz CMOS quadrature modulator (QMOD) for a global system for mobile communications (GSM) transmitter. QMOD consists of two attenuators and two doubly-balanced modulators (DBM's) and fabricated by using 0.35-µm CMOS process. The carrier leakage level of -35.7 dBc and the image rejection level of -45.1 dBc are achieved. It's total chip area is 880 µm550 µm and it consumes 1.0 mA with 3.0 V power supply.

Novel deterministic digital calibration of pipelined ADC has been proposed and analyzed theoretically. Each MDAC is dithered exploiting its inherent redundancy during the calibration. The dither enables fast accurate convergence of calibration without requiring any accurate reference signal and hence with minimum area and power overhead. The proposed calibration can be applied to both the 1.5-bit/stage MDAC and the multi-bit/stage MDAC. Due to its simple structure and algorithm, it can be modified to the background calibration easily. The effectiveness of the proposed calibration has been confirmed by both the extensive simulations and the measurement of the prototype 0.13-µm-CMOS 50-MS/s pipelined ADC using the op-amps with only 37-dB gain. As expected, SNDR and SFDR have improved from 35.5dB to 58.1dB and from 37.4dB to 70.4dB, respectively by the proposed calibration.

A 4th-order programmable continuous-time filter (CTF) for hard-disk-drive (HDD) read channels was developed with 65-nm CMOS process technology. The CTF cutoff frequency and boost are programmable by switching units of the operational trans-conductance amplifier (OTA) banks and the capacitor banks. The switches are operated by lifted local-supply voltage to reduce on-resistance of the transistors. The CTF characteristics were robust against process technology variations and supply voltage and temperature ranges due to the introduction of a digitally assisted compensation scheme with analog auto-tuning circuits and digital calibration sequences. The digital calibration sequences, which fit into the operation sequence of the HDD read channel, compensate for the tuning circuits of the process technology variations, and the tuning circuits compensate for the CTF characteristics over the supply voltage and temperature ranges. As a result, the CTF had a programmability of 100–1000-MHz cutoff frequency and 0–12-dB boost.

This paper describes a CMOS Offset Phase Locked Loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of -163.5 dBc/Hz, the phase error of 0.66rms, and the settling time of 40µs were achieved. The IC was implemented by using 0.35-µm CMOS process. It takes 860µm620µm of total chip area and consumes 17.6 mA with a 3.0 V power supply.

3D ultrasound imagers require low-noise amplifier (LNA) with much lower power consumption and smaller chip area than conventional 2D imagers because of the huge amount of transducer channels. This paper presents a low-power small-size LNA with a novel current-reuse circuitry for 3D ultrasound imaging systems. The proposed LNA is composed of a differential common source amplifier and a source-follower driver which share the current without using inductors. The LNA was fabricated in a 0.18-μm CMOS process with only 0.0056mm2. The measured results show a gain of 21dB and a bandwidth of 9MHz. The proposed LNA achieves an average noise density of 11.3nV/√Hz, and the 2nd harmonic distortion below -40dBc with 0.1-Vpp input. The supply current is 85μA with a 1.8-V power supply, which is competitive with conventional LNAs by finer CMOS process.