A CMOS Offset Phase Locked Loop for a GSM Transmitter

Taizo YAMAWAKI; Masaru KOKUBO; Hiroshi HAGISAWA

A CMOS Offset Phase Locked Loop for a GSM Transmitter

Taizo YAMAWAKI, Masaru KOKUBO, Hiroshi HAGISAWA

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This paper describes a CMOS Offset Phase Locked Loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of -163.5 dBc/Hz, the phase error of 0.66rms, and the settling time of 40µs were achieved. The IC was implemented by using 0.35-µm CMOS process. It takes 860µm620µm of total chip area and consumes 17.6 mA with a 3.0 V power supply.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.2 pp.307-312

Publication Date: 1999/02/25

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Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Taizo YAMAWAKI, Masaru KOKUBO, Hiroshi HAGISAWA, "A CMOS Offset Phase Locked Loop for a GSM Transmitter" in IEICE TRANSACTIONS on Fundamentals, vol. E82-A, no. 2, pp. 307-312, February 1999, doi: .
Abstract: This paper describes a CMOS Offset Phase Locked Loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of -163.5 dBc/Hz, the phase error of 0.66rms, and the settling time of 40µs were achieved. The IC was implemented by using 0.35-µm CMOS process. It takes 860µm620µm of total chip area and consumes 17.6 mA with a 3.0 V power supply.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_307/_p

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@ARTICLE{e82-a_2_307,
author={Taizo YAMAWAKI, Masaru KOKUBO, Hiroshi HAGISAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A CMOS Offset Phase Locked Loop for a GSM Transmitter},
year={1999},
volume={E82-A},
number={2},
pages={307-312},
abstract={This paper describes a CMOS Offset Phase Locked Loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of -163.5 dBc/Hz, the phase error of 0.66rms, and the settling time of 40µs were achieved. The IC was implemented by using 0.35-µm CMOS process. It takes 860µm620µm of total chip area and consumes 17.6 mA with a 3.0 V power supply.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - A CMOS Offset Phase Locked Loop for a GSM Transmitter
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 307
EP - 312
AU - Taizo YAMAWAKI
AU - Masaru KOKUBO
AU - Hiroshi HAGISAWA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - This paper describes a CMOS Offset Phase Locked Loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of -163.5 dBc/Hz, the phase error of 0.66rms, and the settling time of 40µs were achieved. The IC was implemented by using 0.35-µm CMOS process. It takes 860µm620µm of total chip area and consumes 17.6 mA with a 3.0 V power supply.
ER -