A 10 bit 50 MS/s CMOS D/A Converter with 2.7 V Power Supply

Takahiro MIKI; Yasuyuki NAKAMURA; Yoshikazu NISHIKAWA; Keisuke OKADA; Yasutaka HORIBA

A 10 bit 50 MS/s CMOS D/A Converter with 2.7 V Power Supply

Takahiro MIKI, Yasuyuki NAKAMURA, Yoshikazu NISHIKAWA, Keisuke OKADA, Yasutaka HORIBA

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It has become an important subject to realize a high-speed D/A converter with low supply voltage. This paper discusses a 10 bit 50 MS/s CMOS D/A converter with 2.7 V power supply. Reduction of the supply voltage is achieved by developing "saturation-linear" biasing technique in current sources. In this scheme, a grounded transistor in cascode configuration is biased in linear region. High conversion rate is obtained by driving this grounded transistor directly. A charging transistor is also introduced into the current source for accelerating the settling time. The D/A converter is fabricated in a 1 µm CMOS process without using optional process steps. It successfully operates at 50 MS/s with 2.7 V power supply. The circuit techniques discussed here can be easily introduced into half-micron D/A converters.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.5 pp.738-745

Publication Date: 1993/05/25

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Type of Manuscript: Special Section PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits)

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Takahiro MIKI, Yasuyuki NAKAMURA, Yoshikazu NISHIKAWA, Keisuke OKADA, Yasutaka HORIBA, "A 10 bit 50 MS/s CMOS D/A Converter with 2.7 V Power Supply" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 5, pp. 738-745, May 1993, doi: .
Abstract: It has become an important subject to realize a high-speed D/A converter with low supply voltage. This paper discusses a 10 bit 50 MS/s CMOS D/A converter with 2.7 V power supply. Reduction of the supply voltage is achieved by developing "saturation-linear" biasing technique in current sources. In this scheme, a grounded transistor in cascode configuration is biased in linear region. High conversion rate is obtained by driving this grounded transistor directly. A charging transistor is also introduced into the current source for accelerating the settling time. The D/A converter is fabricated in a 1 µm CMOS process without using optional process steps. It successfully operates at 50 MS/s with 2.7 V power supply. The circuit techniques discussed here can be easily introduced into half-micron D/A converters.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_5_738/_p

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@ARTICLE{e76-c_5_738,
author={Takahiro MIKI, Yasuyuki NAKAMURA, Yoshikazu NISHIKAWA, Keisuke OKADA, Yasutaka HORIBA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 10 bit 50 MS/s CMOS D/A Converter with 2.7 V Power Supply},
year={1993},
volume={E76-C},
number={5},
pages={738-745},
abstract={It has become an important subject to realize a high-speed D/A converter with low supply voltage. This paper discusses a 10 bit 50 MS/s CMOS D/A converter with 2.7 V power supply. Reduction of the supply voltage is achieved by developing "saturation-linear" biasing technique in current sources. In this scheme, a grounded transistor in cascode configuration is biased in linear region. High conversion rate is obtained by driving this grounded transistor directly. A charging transistor is also introduced into the current source for accelerating the settling time. The D/A converter is fabricated in a 1 µm CMOS process without using optional process steps. It successfully operates at 50 MS/s with 2.7 V power supply. The circuit techniques discussed here can be easily introduced into half-micron D/A converters.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A 10 bit 50 MS/s CMOS D/A Converter with 2.7 V Power Supply
T2 - IEICE TRANSACTIONS on Electronics
SP - 738
EP - 745
AU - Takahiro MIKI
AU - Yasuyuki NAKAMURA
AU - Yoshikazu NISHIKAWA
AU - Keisuke OKADA
AU - Yasutaka HORIBA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1993
AB - It has become an important subject to realize a high-speed D/A converter with low supply voltage. This paper discusses a 10 bit 50 MS/s CMOS D/A converter with 2.7 V power supply. Reduction of the supply voltage is achieved by developing "saturation-linear" biasing technique in current sources. In this scheme, a grounded transistor in cascode configuration is biased in linear region. High conversion rate is obtained by driving this grounded transistor directly. A charging transistor is also introduced into the current source for accelerating the settling time. The D/A converter is fabricated in a 1 µm CMOS process without using optional process steps. It successfully operates at 50 MS/s with 2.7 V power supply. The circuit techniques discussed here can be easily introduced into half-micron D/A converters.
ER -