Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems

Kwang-Hyun BAEK

doi:10.1093/ietele/e88-c.5.1053

Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems

Kwang-Hyun BAEK

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This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5T_CLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.

Publication: IEICE TRANSACTIONS on Electronics Vol.E88-C No.5 pp.1053-1060

Publication Date: 2005/05/01

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DOI: 10.1093/ietele/e88-c.5.1053

Type of Manuscript: PAPER

Category: Electronic Circuits

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Kwang-Hyun BAEK, "Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems" in IEICE TRANSACTIONS on Electronics, vol. E88-C, no. 5, pp. 1053-1060, May 2005, doi: 10.1093/ietele/e88-c.5.1053.
Abstract: This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5T_CLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.5.1053/_p

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@ARTICLE{e88-c_5_1053,
author={Kwang-Hyun BAEK, },
journal={IEICE TRANSACTIONS on Electronics},
title={Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems},
year={2005},
volume={E88-C},
number={5},
pages={1053-1060},
abstract={This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5T_CLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.},
keywords={},
doi={10.1093/ietele/e88-c.5.1053},
ISSN={},
month={May},}

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TY - JOUR
TI - Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1053
EP - 1060
AU - Kwang-Hyun BAEK
PY - 2005
DO - 10.1093/ietele/e88-c.5.1053
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2005
AB - This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5T_CLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.
ER -