Broadband amplifiers have been used in modern wireless communication systems. However, the accompanying disadvantage is that there is more nonlinear interference in the available operating frequency band. In addition to the in-band intermodulation distortion which affecting adjacent frequency bands the most important is harmonic distortion. In this letter we present a robust and low complex digital harmonic canceling model called cross-disturbing harmonic (CDH) model for broadband power amplifiers (PAs). The approach introducing cross terms is used to enhance the robustness of the model, thereby significantly increase the stability of the system. The CDH model still has excellent performance when actively reducing the number of coefficients. Comparisons are conducted between the CDH model and the other state-of-the-art model called memory polynomial harmonic (MPM) model. Experimental results show that the CDH model can achieve comparable performance as the MPM model but with much fewer (43%) coefficients.

In this work, a measurement-based procedure aimed at deriving a behavioral model of Bulk Current Injection (BCI) probes clamped onto multi-wire cable bundles is proposed. The procedure utilizes the measurement data obtained by mounting the probe onto the calibration jig for model-parameters extraction, and 2D electromagnetic simulations to adapt such parameters to the specific characteristics of the cable bundle under analysis. Outcome of the analysis is a behavioral model which can be easily implemented into the SPICE environment. Without loss of generality, the proposed model is here used to predict the radio-frequency noise stressing the terminal units of a two-wire harness. Model accuracy in predicting the common and differential mode voltages induced by BCI at the line terminals is assessed by EM modeling and simulation of the involved injection setup by the commercial software CST Microwave Studio.

A probing front end circuit (PFE) senses and digitizes voltage noises at in-circuit locations on such as power supply wiring and substrate taps in a chip, with the simplest circuit construction only with a source follower or a unity gain buffer, followed by a latch comparator. The PFE with 2.5V I/O transistors in a 65nm CMOS technology node demonstrates 9.0 ENOB and 60.7dB SFDR in equivalent sampling at 1.0Gs/s, for a sinusoidal waveform of 10MHz with 200mV peak-to-peak amplitude. Behavioral modeling of an entire waveform acquisition system using PFEs includes the statistical variations of reference voltage and sampling timing. The simulation quantitatively explains the measured dynamic properties of on-chip noise monitoring, such as the AC response in SNDR and digitizing throughputs, with the clear dependency on the frequency and amplitude of input waveforms.

An integrated multi-level simulation environment is developed for a highly collision-resistant RFID system. An analog/mixed-signal (AMS) simulator for a circuit-level description of analog front-end power/signal transmission through electro-magnetic coupling is concurrently connected to a tailored software simulator for system-level description of digital back-end processing of TH-CDMA based anti-collision communication. The feasibility of the RFID system in which more than 1,000 transponders can be identified by a single reader in 400 msec is successfuly explored, under a practical presence of field disturbances such as background noises in communication channels as well as variations of electro-magnetic coupling strengths for power transmission.

This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5TCLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.

A systematic and efficient approach is presented to generating simple yet accurate symbolic expressions for transfer functions and characteristics of large linear analog circuits. The approach is based on a compact determinant decision diagram (DDD) representation of exact transfer functions and characteristics. Several key tasks of generating interpretable symbolic expressions--DDD graph simplification, term de-cancellation, and dominant-term generation--are shown to be able to perform linearly by means of DDD graph operations. An efficient algorithm for generating dominant terms is presented based on the concepts of finding the k-shortest paths in a DDD graph. Experimental results show that our approach outperforms other start-of-the-art approaches, and is capable of generating interpretable expressions for typical analog blocks in minutes on modern computer workstations.

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ΔΣADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.