IEICE TRANSACTIONS on Fundamentals
Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring
Summary :
A probing front end circuit (PFE) senses and digitizes voltage noises at in-circuit locations on such as power supply wiring and substrate taps in a chip, with the simplest circuit construction only with a source follower or a unity gain buffer, followed by a latch comparator. The PFE with 2.5V I/O transistors in a 65nm CMOS technology node demonstrates 9.0 ENOB and 60.7dB SFDR in equivalent sampling at 1.0Gs/s, for a sinusoidal waveform of 10MHz with 200mV peak-to-peak amplitude. Behavioral modeling of an entire waveform acquisition system using PFEs includes the statistical variations of reference voltage and sampling timing. The simulation quantitatively explains the measured dynamic properties of on-chip noise monitoring, such as the AC response in SNDR and digitizing throughputs, with the clear dependency on the frequency and amplitude of input waveforms.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2516-2523
- Publication Date
- 2013/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.2516
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
Yuuki ARAGA
Kobe University
Nao UEDA
Kobe University
Yasumasa TAKAGI
Kobe University
Makoto NAGATA
Kobe University
Keyword
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Yuuki ARAGA, Nao UEDA, Yasumasa TAKAGI, Makoto NAGATA, "Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 12, pp. 2516-2523, December 2013, doi: 10.1587/transfun.E96.A.2516.
Abstract: A probing front end circuit (PFE) senses and digitizes voltage noises at in-circuit locations on such as power supply wiring and substrate taps in a chip, with the simplest circuit construction only with a source follower or a unity gain buffer, followed by a latch comparator. The PFE with 2.5V I/O transistors in a 65nm CMOS technology node demonstrates 9.0 ENOB and 60.7dB SFDR in equivalent sampling at 1.0Gs/s, for a sinusoidal waveform of 10MHz with 200mV peak-to-peak amplitude. Behavioral modeling of an entire waveform acquisition system using PFEs includes the statistical variations of reference voltage and sampling timing. The simulation quantitatively explains the measured dynamic properties of on-chip noise monitoring, such as the AC response in SNDR and digitizing throughputs, with the clear dependency on the frequency and amplitude of input waveforms.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2516/_p
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@ARTICLE{e96-a_12_2516,
author={Yuuki ARAGA, Nao UEDA, Yasumasa TAKAGI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring},
year={2013},
volume={E96-A},
number={12},
pages={2516-2523},
abstract={A probing front end circuit (PFE) senses and digitizes voltage noises at in-circuit locations on such as power supply wiring and substrate taps in a chip, with the simplest circuit construction only with a source follower or a unity gain buffer, followed by a latch comparator. The PFE with 2.5V I/O transistors in a 65nm CMOS technology node demonstrates 9.0 ENOB and 60.7dB SFDR in equivalent sampling at 1.0Gs/s, for a sinusoidal waveform of 10MHz with 200mV peak-to-peak amplitude. Behavioral modeling of an entire waveform acquisition system using PFEs includes the statistical variations of reference voltage and sampling timing. The simulation quantitatively explains the measured dynamic properties of on-chip noise monitoring, such as the AC response in SNDR and digitizing throughputs, with the clear dependency on the frequency and amplitude of input waveforms.},
keywords={},
doi={10.1587/transfun.E96.A.2516},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2516
EP - 2523
AU - Yuuki ARAGA
AU - Nao UEDA
AU - Yasumasa TAKAGI
AU - Makoto NAGATA
PY - 2013
DO - 10.1587/transfun.E96.A.2516
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - A probing front end circuit (PFE) senses and digitizes voltage noises at in-circuit locations on such as power supply wiring and substrate taps in a chip, with the simplest circuit construction only with a source follower or a unity gain buffer, followed by a latch comparator. The PFE with 2.5V I/O transistors in a 65nm CMOS technology node demonstrates 9.0 ENOB and 60.7dB SFDR in equivalent sampling at 1.0Gs/s, for a sinusoidal waveform of 10MHz with 200mV peak-to-peak amplitude. Behavioral modeling of an entire waveform acquisition system using PFEs includes the statistical variations of reference voltage and sampling timing. The simulation quantitatively explains the measured dynamic properties of on-chip noise monitoring, such as the AC response in SNDR and digitizing throughputs, with the clear dependency on the frequency and amplitude of input waveforms.
ER -
English
