The plain bend in a pair of differential transmission lines causes a path difference, which leads to differential-to-common mode conversion due to the phase difference. This conversion can cause serious common-mode noise issues. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion and derived the constraint conditions for high-density wiring. To provide sufficient suppression of mode conversion, however, the additional correction was required to make the effective path difference vanish. This paper proposes a practical and straightforward design methodology by using a very tightly coupled bend (decreasing the line width and the line separation of the tightly coupled bend). Full-wave simulations below 20GHz demonstrated that sufficient suppression of the forward differential-to-common mode conversion is successfully achieved as designed. Measurements showed that our design methodology is effective.

This paper describes designing a new pedestrian navigation system using a comprehensive framework called the pedestrian navigation concept reference model (PNCRM). We implement this system as a publicly-available smartphone application and evaluate its positioning performance near Omiya station's western entrance. We also evaluate users' subjective impressions of the system using a questionnaire. In both cases, promising results are obtained, showing that the PNCRM can be used as a tool for designing pedestrian navigation systems, allowing such systems to be created systematically.

This paper presents an automatic hierarchical formal verification method for arithmetic circuits over Galois fields (GFs) which are dedicated digital circuits for GF arithmetic operations used in cryptographic processors. The proposed verification method is based on a combination of a word-level computer algebra procedure with a bit-level PPRM (Positive Polarity Reed-Muller) expansion procedure. While the application of the proposed verification method is not limited to cryptographic processors, these processors are our important targets because complicated implementation techniques, such as field conversions, are frequently used for side-channel resistant, compact and low power design. In the proposed method, the correctness of entire datapath is verified over GF(2m) level, or word-level. A datapath implementation is represented hierarchically as a set of components' functional descriptions over GF(2m) and their wiring connections. We verify that the implementation satisfies a given total-functional specification over GF(2m), by using an automatic algebraic method based on the Gröbner basis and a polynomial reduction. Then, in order to verify whether each component circuit is correctly implemented by combination of GF(2) operations, i.e. logic gates in bit-level, we use our fast PPRM expansion procedure which is customized for handling large-scale Boolean expressions with many variables. We have applied the proposed method to a complicated AES (Advanced Encryption Standard) circuit with a masking countermeasure against side-channel attack. The results show that the proposed method can verify such practical circuit automatically within 4 minutes, while any single conventional verification methods fail within a day or even more.

We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64dB is achievable at an input signal frequency of 10kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses.

Function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work has focused on two-stage function speculation and thus lacks a systematic way to address the challenge of the multistage function speculation approach. This paper proposes a multistage function speculation with adaptive predictors and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results on the fabricated chips show that the proposed adder's delay and area have a logarithmic and linear relationship with its bit number, respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6-17% area reduction under different bit lengths.

Turbo mode, which accelerates many applications without major change of existing systems, is widely used in commercial processors. Since time duration or powerfulness of turbo mode depends on peak temperature of a processor chip, reducing the peak temperature can reinforce turbo mode. This paper presents that adding small amount of hardware allows microprocessors to reduce the peak temperature drastically and then to reinforce turbo mode successfully. Our approach is to find out a few small units that become heat sources in a processor and to appropriately duplicate them for reduction of their power density. By duplicating the limited units and using the copies evenly, the processor can show significant performance improvement while achieving area-efficiency. The experimental result shows that the proposed method achieves up to 14.5% of performance improvement in exchange for 2.8% of area increase.

Superconducting Single-Flux-Quantum (SFQ) devices have been paid much attention as alternative devices for digital circuits, because of their high switching speed and low power consumption. For large-scale circuit design, the role of computer-aided design environment is significant. As the characteristics of the SFQ devices are different from conventional devices, a new design environment is required. In this paper, we propose a new timing-aware circuit description method which can be used for SFQ circuit design. Based on the description and the dedicated algorithms we have been developing for SFQ logic circuit design, we propose an integrated design flow for SFQ logic circuits. We have designed a circuit using our developed design tools along with the design flow and demonstrated the correct operation.

Dependence of within-die delay variations on power supply voltage (VDD) is measured down to 0.4 V. The VDD dependence of the within-die delay variation of manual layout and irregular auto place and route (P&R) layout are compared for the first time. The measured relative delay (=sigma/average) variation difference between the manual layout and the P&R layout decreases from 1.56% to 0.07% with reducing VDD from 1.2 V to 0.4 V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low VDD.

We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter implemented in a 0.18 µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.

In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.

The process of designing analogue circuits is formulated as a controlled dynamic system. For analysis of such system's properties it is suggested to use the concept of Lyapunov's function for a dynamic system. Various forms of Lyapunov's function are suggested. Analyzing the behavior of Lyapunov's function and its first derivative allowed us to determine significant correlation between this function's properties and processor time used to design the circuit. Numerical results prove the possibility of forecasting the behavior of various designing strategies and processor time based on the properties of Lyapunov's function for the process of designing the circuit.

Although much research effort has been devoted to the minimization of total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by it. In this paper, we propose an opposite-phase clock scheme to reduce the peak current incurred by the clock tree. Our basic idea is to balance the charging and discharging activities. According to the output operation, the clock buffers that transit simultaneously are divided into two groups: half of the clock buffers transit at the same phase of the clock source, while the other half transit at the opposite phase of the clock source. As a consequence, the opposite-phase clock scheme significantly reduces the peak current caused by the clock tree. Experimental data show that our approach can be applied at different design stages in the existing design flow.

Web services (WS, hereafter) paradigm has attained such a relevance in both the academic and the industry world that the vision of the Internet has evolved from being considered as a mere repository of data to become the underlying infrastructure on which organizations' strategic business operations are being deployed [1]. Security is a key aspect if WS are to be generally accepted and adopted. In fact, over the past years, the most important consortiums of the Internet, like IETF, W3C or OASIS, have produced a huge number of WS-based security standards. Despite this spectacular growth, a development process that facilitates the systematic integration of security into all subprocesses of WS-based software development life-cycle does not exist. Eventually, this process should guide WS-based software developers in the specification of WS-based security requirements, the design of WS-based security architectures, and the deployment of the most suitable WS security standards. In this article, we will briefly present a process of this type, named PWSSec (Process for Web Services Security), and the artifacts used during the elicitation activity, which belongs to the subprocess WSSecReq aimed at producing a WS-based security requirement specification.

Various trajectories of design, arising from the new methodology of analog network design, are analyzed. Several major criteria suggested for optimal selection of initial approximation to the design process permit the minimization of computer time. The initial approximation point is selected with regard to the previously revealed effect of acceleration of the design process. The concept of separatrix is defined making it possible to determine the optimal position of the initial approximation. The numerical results obtained for passive and active networks prove the possibility of optimal choice of the initial point in design process.

We discuss a new design methodology of polynomial neural networks (PNN) in the framework of genetic algorithm (GA). The PNN is based on the ideas of group method of data handling (GMDH). Each node in the network is very flexible and can carry out polynomial type mapping between input and output variables. But the performances of PNN depend strongly on the number of input variables available to the model, the number of input variables, and the type (order) of the polynomials to each node. In this paper, GA is implemented to better use the optimal inputs and the order of polynomial in each node of PNN. The appropriate inputs and order are evolved accordingly and are tuned gradually throughout the GA iterations. We employ a binary coding for encoding key factors of the PNN into the chromosomes. The chromosomes are made of three sub-chromosomes which represent the order, number of inputs, and input candidates for modeling. To construct model by using significant approximation and generalization, we introduce the fitness function with a weighting factor. Comparisons with other modeling methods and conventional PNN show that the proposed design method offers encouraging advantages and better performance.

This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5TCLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.

The purpose of this paper is to present a rapid prototyping flow for the development of a wireless LAN system. The proposed system flow that was used for the development of the prototype is based on the use of UML (Unified Modeling Language). The UML and its real-time extensions are used to help the development phases of the prototype, mainly in the specification, co-simulation and validation of the design. The target of the development that was carried out with the application of the UML-based methodology is the implementation of an access point for a HIPERLAN/2 wireless network. Apart from the presentation of the UML-based system design methodology the paper also presents the application of the methodology for the implementation of the system prototype, the detailed software development and the results of the development.

This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.

On the basis of generalized theory of system design the behavior of the different design trajectories in the design phase space was analyzed. An additional acceleration effect of the design process has been discovered by the analysis of various design strategies with different initial points. This effect can be understood well on the basis of the elaborated design methodology by means of the different design trajectory analysis. This effect is displayed for all analyzed circuits and it reduces additionally the total computer time for the system design.

The EMC-adequate design of microelectronic systems includes all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include a growing system complexity, high integration levels and higher operating speeds at all levels of integration (chip, MCM, printed circuit board and system). The growing complexity, denser design and higher speed all lead to a substantial increase in EMC problems and accordingly the design time. EMC is not commonly accepted as a vital topic in microelectronic design. Microelectronic designers often are of the opinion that EMC is limited to electrical and electronic systems and the mandatory product regulations instead of setting requirements also for the integrated circuit they are designing. In this contribution a concept for an EMC-adequate design of electronic systems will be introduced. This concept is based on a generalized development process to integrate EMC-constraints into the system design. A prototype of an environment to analyse signal integrity effects on PCB based on a workflow oriented integration approach will be presented. Based on this approach the generation of user specific design and analysis environments including various set of EMC-tools is possible.