IEICE TRANSACTIONS on Communications
A Software Radio Receiver with Direct Conversion and Its Digital Processing
Summary :
This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E85-B No.12 pp.2741-2749
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Software Defined Radio Technology and Its Applications)
- Category
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Robert MORELOS-ZARAGOZA, Shinichiro HARUYAMA, Masayoshi ABE, Noboru SASHO, Lachlan B. MICHAEL, Ryuji KOHNO, "A Software Radio Receiver with Direct Conversion and Its Digital Processing" in IEICE TRANSACTIONS on Communications,
vol. E85-B, no. 12, pp. 2741-2749, December 2002, doi: .
Abstract: This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e85-b_12_2741/_p
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@ARTICLE{e85-b_12_2741,
author={Robert MORELOS-ZARAGOZA, Shinichiro HARUYAMA, Masayoshi ABE, Noboru SASHO, Lachlan B. MICHAEL, Ryuji KOHNO, },
journal={IEICE TRANSACTIONS on Communications},
title={A Software Radio Receiver with Direct Conversion and Its Digital Processing},
year={2002},
volume={E85-B},
number={12},
pages={2741-2749},
abstract={This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Software Radio Receiver with Direct Conversion and Its Digital Processing
T2 - IEICE TRANSACTIONS on Communications
SP - 2741
EP - 2749
AU - Robert MORELOS-ZARAGOZA
AU - Shinichiro HARUYAMA
AU - Masayoshi ABE
AU - Noboru SASHO
AU - Lachlan B. MICHAEL
AU - Ryuji KOHNO
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E85-B
IS - 12
JA - IEICE TRANSACTIONS on Communications
Y1 - December 2002
AB - This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.
ER -
English
