Multistage Function Speculation Adders

Yinan SUN; Yongpan LIU; Zhibo WANG; Huazhong YANG

doi:10.1587/transfun.E98.A.954

Multistage Function Speculation Adders

Yinan SUN, Yongpan LIU, Zhibo WANG, Huazhong YANG

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Summary :

Function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work has focused on two-stage function speculation and thus lacks a systematic way to address the challenge of the multistage function speculation approach. This paper proposes a multistage function speculation with adaptive predictors and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results on the fabricated chips show that the proposed adder's delay and area have a logarithmic and linear relationship with its bit number, respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6-17% area reduction under different bit lengths.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.4 pp.954-965

Publication Date: 2015/04/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E98.A.954

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

Authors

Yinan SUN
  Tsinghua University
Yongpan LIU
  Tsinghua University
Zhibo WANG
  Tsinghua University
Huazhong YANG
  Tsinghua University

Keyword

multistage function speculation, variable latency adder, design methodology

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Yinan SUN, Yongpan LIU, Zhibo WANG, Huazhong YANG, "Multistage Function Speculation Adders" in IEICE TRANSACTIONS on Fundamentals, vol. E98-A, no. 4, pp. 954-965, April 2015, doi: 10.1587/transfun.E98.A.954.
Abstract: Function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work has focused on two-stage function speculation and thus lacks a systematic way to address the challenge of the multistage function speculation approach. This paper proposes a multistage function speculation with adaptive predictors and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results on the fabricated chips show that the proposed adder's delay and area have a logarithmic and linear relationship with its bit number, respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6-17% area reduction under different bit lengths.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.954/_p

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@ARTICLE{e98-a_4_954,
author={Yinan SUN, Yongpan LIU, Zhibo WANG, Huazhong YANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Multistage Function Speculation Adders},
year={2015},
volume={E98-A},
number={4},
pages={954-965},
abstract={Function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work has focused on two-stage function speculation and thus lacks a systematic way to address the challenge of the multistage function speculation approach. This paper proposes a multistage function speculation with adaptive predictors and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results on the fabricated chips show that the proposed adder's delay and area have a logarithmic and linear relationship with its bit number, respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6-17% area reduction under different bit lengths.},
keywords={},
doi={10.1587/transfun.E98.A.954},
ISSN={1745-1337},
month={April},}

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TY - JOUR
TI - Multistage Function Speculation Adders
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 954
EP - 965
AU - Yinan SUN
AU - Yongpan LIU
AU - Zhibo WANG
AU - Huazhong YANG
PY - 2015
DO - 10.1587/transfun.E98.A.954
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2015
AB - Function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work has focused on two-stage function speculation and thus lacks a systematic way to address the challenge of the multistage function speculation approach. This paper proposes a multistage function speculation with adaptive predictors and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results on the fabricated chips show that the proposed adder's delay and area have a logarithmic and linear relationship with its bit number, respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6-17% area reduction under different bit lengths.
ER -