This paper presents the design of a CMOS RF Power Detector (PD) using 0.18 µm standard CMOS technology. The PD is an improved unbalanced source coupled pair incorporating an output differential amplifier and sink current steering. It realizes an input detectable power range of -30 to -20 dBm over 0.1-1 GHz. Also it shows a maximum data rate of 30 Mbps with 2 pF output loading under OOK modulation. The overall current consumption is 1.9 mA under a 1.5 V supply.

This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35 µm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70 mW at 3.3 V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.

This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below 0.5 LSB and that the settling time after the output current mirror is below 12 ns. Although the proposed IDAC architecture was designed for a BMLD chip, the design concept is generic and can be applied for developing other monotonic high-speed current-mode DACs.

This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.

A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with on-chip terminated resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, furthermore, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 µm 2-poly 3-metal CMOS technology, and it occupies 1350 µm750 µm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.