In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an auto-switching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28 mm2 in 0.18 µm CMOS technology.

A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with on-chip terminated resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, furthermore, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 µm 2-poly 3-metal CMOS technology, and it occupies 1350 µm750 µm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.