A Fully Integrated Current-Steering 10-b CMOS D/A Converter with On-Chip Terminated Resistors

Sanghoon HWANG; Minkyu SONG

A Fully Integrated Current-Steering 10-b CMOS D/A Converter with On-Chip Terminated Resistors

Sanghoon HWANG, Minkyu SONG

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A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with on-chip terminated resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, furthermore, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 µm 2-poly 3-metal CMOS technology, and it occupies 1350 µm750 µm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.12 pp.2179-2185

Publication Date: 2004/12/01

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Sanghoon HWANG, Minkyu SONG, "A Fully Integrated Current-Steering 10-b CMOS D/A Converter with On-Chip Terminated Resistors" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 12, pp. 2179-2185, December 2004, doi: .
Abstract: A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with on-chip terminated resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, furthermore, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 µm 2-poly 3-metal CMOS technology, and it occupies 1350 µm750 µm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_12_2179/_p

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@ARTICLE{e87-c_12_2179,
author={Sanghoon HWANG, Minkyu SONG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fully Integrated Current-Steering 10-b CMOS D/A Converter with On-Chip Terminated Resistors},
year={2004},
volume={E87-C},
number={12},
pages={2179-2185},
abstract={A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with on-chip terminated resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, furthermore, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 µm 2-poly 3-metal CMOS technology, and it occupies 1350 µm750 µm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Fully Integrated Current-Steering 10-b CMOS D/A Converter with On-Chip Terminated Resistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 2179
EP - 2185
AU - Sanghoon HWANG
AU - Minkyu SONG
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2004
AB - A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with on-chip terminated resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, furthermore, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 µm 2-poly 3-metal CMOS technology, and it occupies 1350 µm750 µm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.
ER -