This article reviews the author’s group research achievements in analog/mixed-signal circuit and system area with introduction of how they came up with the ideas. Analog/mixed-signal circuits and systems have to be designed as well-balanced in many aspects, and coming up ideas needs some experiences and discussions with researchers. It is also heavily dependent on researchers. Here, the author’s group own experiences are presented as well as their research motivations.

In this paper, a nonlinear quantized precoding scheme for low-resolution digital-analog converters (DACs) in a massive multiple-input multiple-output (MIMO) system is proposed. The nonlinear quantized precoding determines transmit antenna outputs with a transmit symbol and channel state information. In a full-digital massive MIMO system, low-resolution DACs are used to suppress power consumption. Conventional precoding algorithms for low-resolution DACs do not optimize transmit antenna gains individually. Thus, in this paper, a precoding scheme that optimizes individual transmit antenna gains as well as the DAC outputs is proposed. In the proposed scheme, the subarray of massive MIMO antennas is treated virtually as a single antenna element. Numerical results obtained through computer simulation show that the proposed precoding scheme achieves bit error rate performance close to that of the conventional precoding scheme with much smaller antenna gains on a CDL-A channel.

In this paper, a non-linear precoding algorithm with low out-of-band (OOB) radiation is proposed for massive multiple-input multiple-output (MIMO) systems. Massive MIMO sets more than one hundred antennas at each base station to achieve higher spectral efficiency and throughput. Full digital massive MIMO may constrain the resolution of digital-to-analog converters (DACs) since each DAC consumes a large amount of power. In massive MIMO systems with low resolution DACs, designing methods of DAC output signals by nonlinear processing are being investigated. The conventional scheme focuses only on a sum rate or errors in the received signals and so triggers large OOB radiation. This paper proposes an optimization criterion that takes OOB radiation power into account. Gibbs sampling is used as an algorithm to find sub-optimal solutions given this criterion. Numerical results obtained through computer simulation show that the proposed criterion reduces mean OOB radiation power by a factor of 10 as compared with the conventional criterion. The proposed criterion also reduces OOB radiation while increasing the average sum rate by optimizing the weight factor for the OOB radiation. As a result, the proposed criterion achieves approximately 1.3 times higher average sum rates than an error-based criterion. On the other hand, as compared with a sum rate based criterion, the throughput on each subcarrier shows less variation which reduces the number of link adaptation options needed although the average sum rate of the proposed criterion is smaller.

The sum rate performance of nonlinier quantized precoding using Gibbs sampling are evaluated in a massive multiuser multiple-input multiple-output (MU-MIMO) system in this paper. Massive MU-MIMO is a key technology to handle the growth of data traffic. In a full digital massive MU-MIMO system, however, the resolution of digital-to-analogue converters (DACs) in transmit antenna branches have to be low to yield acceptable power consumption. Thus, a combinational optimization problem is solved for the nonlinier quantized precoding to determine transmit signals from finite alphabets output from low resolution DACs. A conventional optimization criterion minimizes errors between desired signals and received signals at user equipments (UEs). However, the system sum rate may decrease as it increases the transmit power. This paper proposes two optimization criteria that take the transmit power into account in order to maximize the sum rate. Mixed Gibbs sampling is applied to obtain the suboptimal solution of the nonlinear optimization problem. Numerical results obtained through computer simulations show that the two proposed criteria achieve higher sum rates than the conventional criterion. On the other hand, the sum rate criterion achieves the largest sum rate while it leads to less throughputs than the MMSE criterion on approximately 60% of subcarriers.

Redactable signature allows anyone to remove parts of a signed message without invalidating the signature. The need to prove the validity of digital documents issued by governments is increasing. When governments disclose documents, they must remove private information concerning individuals. Redactable signature is useful for such a situation. However, in most redactable signature schemes, to remove parts of the signed message, we need pieces of information for each part we want to remove. If a signed message consists of ℓ elements, the number of elements in an original signature is at least linear in ℓ. As far as we know, in some redactable signature schemes, the number of elements in an original signature is constant, regardless of the number of elements in a message to be signed. However, these constructions have drawbacks in that the use of the random oracle model or generic group model. In this paper, we construct an efficient redactable signature to overcome these drawbacks. Our redactable signature is obtained by combining set-commitment proposed in the recent work by Fuchsbauer et al. (JoC 2019) and digital signatures.

C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.

A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s·2(SFDR/6)/W. A proof-of-concept chip with an active area of only 0.22mm2 was measured in prototypes encapsulated in a 144-pins low profile quad flat package.

In the present paper, we propose a novel high-resolution analog-to-digital converter (ADC) for low-power biomedical analog front-ends, which we call the successive stochastic approximation ADC. The proposed ADC uses a stochastic flash ADC (SF-ADC) to realize a digitally controlled variable-threshold comparator in a successive-approximation-register ADC (SAR-ADC), which can correct errors originating from the internal digital-to-analog converter in the SAR-ADC. For the residual error after SAR-ADC operation, which can be smaller than thermal noise, the SF-ADC uses the statistical characteristics of noise to achieve high resolution. The SF-ADC output for the residual signal is combined with the SAR-ADC output to obtain high-precision output data using the supervised machine learning method.

A 12-bit 1.25MS/s cyclic analog-to-digital converter (ADC) is designed and fabricated in 90nm CMOS technology, and only occupies an active area as small as 0.037mm2. The proposed ADC is composed of a non-binary AD convertion stage, and a on-chip non-binary-to-binary digital block includes a built-in radix-value self-estimation scheme. Therefore, althouh a non-binary convertion architechture is adopted, the proposed ADC is the same as other stand-alone binary ADCs. The redundancy of non-binary 1-bit/step architecture relaxes the accuracy requirement on analog components of ADC. As a result, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density Metal-Oxide-Metal (MOM) capacitors can be used to achieve a small chip area. Furthermore, the novel radix-value self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 62.3dB using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The proposed ADC dissipated 490µW in analog circuits at 1.4V power supply and 1.25Msps (20MHz clocking). The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz sinusoidal input.

We propose a synthesis and automatic layout method for mixed-signal circuits with high regularity. As the first step of this research, a resistive digital-to-analog converter (RDAC) is presented. With a size calculation routine, the area of this RDAC is minimized while satisfying the required matching precision without any optimization loops. We propose to partition the design into slices comprising of both analog and digital cells. These cells are programmed to be synthesized as similar as custom P-Cells based on the calculation above, and automatically laid out to form one slice cell. To synthesize digital circuits, without using digital standard cell library, we propose a versatile unit digital block consisting of 8 transistors. With one or several blocks, the transistors' interconnections are programmed in the units to realize various logic gates. By using this block, the slice shapes are aligned so that the layout space in between the slices are minimized. The proposed mixed-signal slice-based partition facilitates the place-and-route of the whole RDAC. The post-layout simulation shows that the generated 9-bit RDAC achieves 1GHz sampling frequency, -0.11/0.09 and -0.30/0.75 DNL and INL, respectively, 3.57mW power consumption, and 0.0038mm2 active area.

Pulse Pairs (PPs) generated by Distance Measure Equipment (DME) cause severe interference on L-band Digital Aeronautical Communication System type 1 (L-DACS1) which is based on Orthogonal Frequency Division Multiplexing (OFDM). In this paper, a novel and practical PP mitigation approach is proposed. Different from previous work, it adopts only time domain methods to mitigate interference, so it will not affect the subsequent signal processing in frequency domain. At the receiver side, the proposed approach can precisely reconstruct the deformed PPs (DPPs) which are often overlapped and have various parameters. Firstly, a filter bank and a correlation scheme are jointly used to detect non-overlapped DPPs, also a weighted average scheme is used to automatically measure the waveform of DPP. Secondly, based on the measured waveform, sparse estimation is used to estimate the precise positions of DPPs. Finally, the parameters of each DPP are estimated by a non-linear estimator. The key point of this step is, a piecewise linear model is used to approximate the non-linear carrier frequency of each DPP. Numerical simulations show that comparing with existing work, the proposed approach is more robust, closer to interference free environment and its Bit Error Rate is reduced by about 10dB.

A novel dynamic element matching (DEM) method, called binary-tree random DEM (BTR-DEM), is presented for a Nyquist-rate current-steering digital-to-analog converter (DAC). By increasing or decreasing the number of unit current sources randomly at the same time, the BTR-DEM encoding reduces switch transition glitches. A 5-bit current-steering DAC with the BTR-DEM technique is implemented in a 65-nm CMOS technology. The measured spurious free dynamic range (SFDR) attains 42 dB for a sample rate of 100 MHz and shows little dependence on signal frequency.

Novel deterministic digital calibration of pipelined ADC has been proposed and analyzed theoretically. Each MDAC is dithered exploiting its inherent redundancy during the calibration. The dither enables fast accurate convergence of calibration without requiring any accurate reference signal and hence with minimum area and power overhead. The proposed calibration can be applied to both the 1.5-bit/stage MDAC and the multi-bit/stage MDAC. Due to its simple structure and algorithm, it can be modified to the background calibration easily. The effectiveness of the proposed calibration has been confirmed by both the extensive simulations and the measurement of the prototype 0.13-µm-CMOS 50-MS/s pipelined ADC using the op-amps with only 37-dB gain. As expected, SNDR and SFDR have improved from 35.5dB to 58.1dB and from 37.4dB to 70.4dB, respectively by the proposed calibration.

Proof-of-concept cyclic analog-to-digital converters (ADCs) have been designed and fabricated in 90-nm CMOS technology. The measurement results of an experimental prototype demonstrate the effectiveness of the proposed switched-capacitor (SC) architecture to realize a non-binary ADC based on β expansion. Different from the conventional binary ADC, a simple 1-bit/step structure for an SC multiplying digital-to-analog converter (MDAC) is proposed to present residue amplification by β (1 < β < 2). The redundancy of non-binary ADCs with radix β tolerates the non-linear conversion errors caused by the offsets of comparators, the mismatches of capacitors, and the finite DC gains of amplifiers, which are used in the MDAC. We also employed a radix value estimation algorithm to obtain an effective value of β for non-binary encoding; it can be realized by merely adding a simple conversion sequence and digital circuits. As a result, the power penalty of a high-gain wideband amplifier and the required accuracy of the circuit elements for a high-resolution ADC were largely relaxed so that the circuit design was greatly simplified. The implemented ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 60.44dB, even with an op-amp with a poor DC gain (< 50dB) while dissipating 780µW in analog circuits at 1.4V and occupying an active area of 0.25 × 0.26mm2.

This paper describes algorithms for generating low intermodulation-distortion (IMD) two-tone sinewaves, for such as communication application ADC testing, using an arbitrary waveform generator (AWG) or a multi-bit ΣΔ DAC inside an SoC. The nonlinearity of the DAC generates distortion components, and we propose here eight methods to precompensate for the IMD using DSP algorithms and produce low-IMD two-tone signals. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of our approach.

This paper proposes a pipeline analog-to-digital converter (ADC) with non-binary encoding technique based on β-expansion. By using multiply-by-β switched-capacitor (SC) multiplying digital-to-analog converter (MDAC) circuit, our proposed ADC is composed by radix-β (1 < β < 2) 1 bit pipeline stages instead of using the conventional radix-2 1.5 bit/1 bit pipeline stages to realize non-binary analog-to-digital conversion. Also with proposed β-value estimation algorithm, there is not any digital calibration technique is required in proposed pipeline ADC. The redundancy of non-binary ADC tolerates not only the non-ideality of comparator, but also the mismatch of capacitances and the gain error of operational amplifier (op-amp) in MDAC. As a result, the power hungry high gain and wide bandwidth op-amps are not necessary for high resolution ADC, so that the reliability-enhanced pipeline ADC with simple amplifiers can operate faster and with lower power. We analyse the β-expansion of AD conversion and modify the β-encoding technique for pipeline ADC. In our knowledge, this is the first proposal architecture for non-binary pipeline ADC. The reliability of the proposed ADC architecture and β-encoding technique are verified by MATLAB simulations.

A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

A new training algorithm for the chaotic Adachi Neural Network (AdNN) is investigated. The classical training algorithm for the AdNN and it's variants is usually a “one-shot” learning, for example, the Outer Product Rule (OPR) is the most used. Although the OPR is effective for conventional neural networks, its effectiveness and adequateness for Chaotic Neural Networks (CNNs) have not been discussed formally. As a complementary and tentative work in this field, we modified the AdNN's weights by enforcing an unsupervised Hebbian rule. Experimental analysis shows that the new weighted AdNN yields even stronger dynamical associative memory and pattern recognition phenomena for different settings than the primitive AdNN.

The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.10.13 mm2.

In Digital Library (DL) applications, digital book clustering is an important and urgent research task. However, it is difficult to conduct effectively because of the great length of digital books. To do the correct clustering for digital books, a novel method based on probabilistic topic model is proposed. Firstly, we build a topic model named LDAC. The main goal of LDAC topic modeling is to effectively extract topics from digital books. Subsequently, Gibbs sampling is applied for parameter inference. Once the model parameters are learned, each book is assigned to the cluster which maximizes the posterior probability. Experimental results demonstrate that our approach based on LDAC is able to achieve significant improvement as compared to the related methods.