How the Author’s Group Came Up with Ideas in Analog/Mixed-Signal Circuit and System Area

Haruo KOBAYASHI

Summary :

This article reviews the author’s group research achievements in analog/mixed-signal circuit and system area with introduction of how they came up with the ideas. Analog/mixed-signal circuits and systems have to be designed as well-balanced in many aspects, and coming up ideas needs some experiences and discussions with researchers. It is also heavily dependent on researchers. Here, the author’s group own experiences are presented as well as their research motivations.

• Publication: IEICE TRANSACTIONS on Fundamentals Vol.E107-A No.5 pp.681-699
• Publication Date: 2024/05/01
• Publicized: 2023/12/07
• Online ISSN: 1745-1337
• DOI: 10.1587/transfun.2023GCI0002
• Type of Manuscript: Special Section INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics)

1.  Introduction

This article reviews the author’s group research achievements in analog/mixed-signal (AMS) circuit and system area with introduction of how they came up with the ideas as well as the research motivations. Many of their approaches are based on signal processing algorithms, control theory and mathematics, which are different from other AMS IC design researchers, though their practical industry applications are taken into account in many cases. AMS circuits and systems have to be designed as well-balanced in many aspects, and design trade-off is an important concept. Coming up ideas needs some experiences and discussions with researchers both in academia and industry. It is also heavily dependent on researchers themselves. Here, the author’s group own experiences are presented as well as their research motivations [1]-[7].

In Sect. 2, circuits related to resistor and capacitor networks are shown. In Sects. 3, 4, waveform sampling technologies and Nyquist-rate DACs are introduced respectively. In Sects. 5, 6, 7, successive-approximation-register (SAR) ADCs with redundancy, time-interleaved ADCs, and time-to-digital converters (TDCs) are described. In Sects. 8, 9, \(\Delta\Sigma\) ADC/DAC/TDC and dynamic element matching techniques are shown, while in Sect. 10, other research results are summarized. Section 11 concludes the paper.

All of the cited references in this paper are from the author’s group and for the technical details, the reader can refer to them.

2.  Resistor and Capacitor Networks

2.1  Spatial and Temporal Dynamics of Active Resistor Network

A long time ago, the author was involved in the research for an analog image processing neuro-chip or vision chip which consisted of positive and negative resistors (i.e., active resistors) (Fig. 1) [8]-[10], and the following circuit theorem was derived [11], [12]:

“For uniform active networks, the spatial and temporal stability conditions are equivalent.”

Fig. 1  Active resistor network with positive and negative resistors [9].

Its generalization to non-uniform networks is discussed in [13], [14].

Triggered by this research, the author became interested in the resistor network, and his group were involved in extension and non-ideality analysis of R-2R ladder DAC and Hopfield network. Also, the research for the circulant active resistor network dynamics in [12] leads to the RC polyphase filter because it has the circulant structure.

2.2  General Resistor Network DAC

We have performed design and analysis of DACs based on the non-uniform current division resistive ladder, and came up with a new configuration DAC with segmentation of binary, quaternary and unary resistive-ladders, which enables two times gain with equivalent chip area and current sources to the conventional DAC (Fig. 2). Also, our simulation showed that the DNL deviation of the proposed one is a little better than the conventional one [15], [16].

Fig. 2  Proposed resistor ladder DAC with binary, quaternary and unary combination [15] ©IEEE.

Further, we investigated a systematic configuration method of resistor ladder networks for N-ary DACs, by generalizing the configuration of the conventional R-2R DAC [17].

Notice that the capacitor-type DAC is popular due to low power, but still the resistor-type DAC is advantageous in some applications, such as programmable DC voltage generator thanks to no requirement for switching.

2.3  RC Polyphase Filter and Hilbert Filter

About 20 years ago, the author heard a presentation from Katholieke Universiteit Leuven group at ISSCC; there an RC polyphase filter and its curious behavior were shown. Then he analyzed it using complex signal processing and circulant matrix theories [7], [18], [19].

After several years, an adjunct professor of Gunma University introduced a digital Hilbert filter at his class, and then the author had an intuition that the RC polyphase filter has characteristics as a complex analog Hilbert filter. We found that phase characteristics of the RC polyphase filter have the same as those of the Hilbert filter. Also, its gain characteristics can be approximated as the Hilbert filter; as its order becomes higher, its gain characteristics become closer to the ideal Hilbert filter (Fig. 3) [20].

Fig. 3  First-order RC polyphase network (left) and its gain characteristics (right) [20] ©IEEE.

As far as the author investigated, the RC polyphase filter can be the best approximated to the Hilbert filter, compared to other complex analog filters.

2.4  Explicit Transfer Function Derivation of High-Order RC Polyphase Filter

The direct derivation of the transfer function of a high-order RC polyphase filter is very complicated with hand calculation. However, one of Ph.D. course students did it relatively easily [21], [22]. Its point is to denote internal node voltages V, \(j\)V, \(-\)V, \(-j\)V instead of V\(_{\rm I+}\), V\(_{\rm Q+}\), V\(_{\rm I-}\), V\(_{\rm Q-}\) in general form (Fig. 4).

Fig. 4  High-order RC polyphase network [21] ©IEEE.

2.5  Resistor and Capacitor Hopfield Network Asynchronous SAR ADCs

The Hopfield network was proposed a long time ago, but it has not been widely used in practice. On the other hand, recently an asynchronous SAR ADC becomes popular. These motivated us to revisit the Hopfield network. Then we came up with an asynchronous SAR ADC with parallel comparators and switched capacitor configuration based on asymmetric Hopfield network [23]. In principle, the original asymmetric Hopfield resistor network can realize an ADC. However, it requires many resistors with giga or even tera-order \(\Omega\). Hence, we investigated to replace the huge resistors with switched capacitor circuits (Fig. 5).

Fig. 5  Asymmetric Hopfield network with resistors (left) and switched capacitor circuit (right) [23].

The proposed N-bit SAR ADC uses N comparators operating in parallel and asynchronously without SAR logic and an internal high-frequency clock. Each lower-bit comparator can operate by look-ahead of its higher-bit comparator results for high speed, and its AD conversion latency is only one or two clock cycles.

3.  Waveform Sampling Technologies

The author was involved in the research for wideband measurement and test systems, and his group investigated wideband waveform sampling technologies (Fig. 6). In this section, their research results are introduced [1].

Fig. 6  Waveform sampling.

3.1  Residue Sampling

ADC and DAC are considered as division and multiplication operations. On the other hand, waveform sampling causes spectrum folding which is similar to but different from division operation in frequency domain.

The author’s group found that sampling of a complex sinusoidal signal (“cosine + j sine” signal) can realize “frequency division” operation (Fig. 7), and we came up with a high-frequency signal estimation circuit using multiple low-frequency sampling circuits following an analog Hilbert filter (RC polyphase filter) and ADCs (Fig. 8) [24], [25]; here the sampling frequencies are relatively prime.

Fig. 7  Residue frequency generation for complex signal \(\rm \cos(2\pi t) + j \sin(2\pi t)\) using sampling [25] ©IEEE.

Fig. 8  Residue sampling system [25] ©IEEE.

A sinusoidal signal with high frequency is provided as an input signal. Then cosine and sine signals with the same frequency are generated with an analog Hilbert filter and they are fed into sampling circuits with different and low sampling frequencies. Their analog outputs are AD converted and for their digital outputs, complex FFTs are performed. The input signal frequency can be estimated from the residue frequencies and the residue number theory: the property of one-to-one mapping between the original number and its residue numbers obtained by division of relatively prime numbers are the key.

The frequency estimation resolution becomes finer as the number of FFT data is increased. Also, we investigated its application to AMS IC testing by collaborating with an automatic test equipment (ATE) manufacturer [26].

3.2  Golden Ratio and Metallic Ratio Sampling

The author learned “waveform missing phenomena” in equivalent-time sampling systems, such as sampling oscilloscopes. Then he tried to find the efficient waveform acquisition condition of the relationship between the sampling clock frequency and the sinusoidal input frequency, which does not cause the phenomena. One of his students found by extensive simulations that the golden ratio (1.6180..) is the most efficient for avoiding the waveform missing phenomena (Fig. 9), and we analyzed its effectiveness in theory and simulation [27].

Fig. 9  Golden ratio sampling and uniform distribution of its sampling points [28] ©IEEE.

As its extension, we investigated metallic ratio sampling of the sampling frequency and the input frequency, which also realizes efficient waveform acquisition. Further several interesting properties of the metallic ratio sampling in the view point of the integer theory were found [28].

These results can be utilized in several LSI testing applications such as ADC histogram test [29] because there the sampling clock and the input signal can be controlled intentionally. Also, the golden ratio and metallic ratio sampling techniques can be used for pseudo random signal generation targeted for Monte Carlo simulations [30].

3.3  Non-Ideality Analysis of Waveform Sampling

Sampling jitter is a serious problem for wideband waveform acquisition (Fig. 10), and high-frequency electronic measurement instrument companies are interested in this issue. Our study on the jitter effect was motivated to realize a high-speed track-hold circuit such as in [31].

Fig. 10  Jitter effects to waveform sampling [33].

Exact noise power \((P_j)\) and SNR degradation due to sampling jitter are derived in Eqs. (1), (2) assuming that the jitter (\(\varepsilon\)n) follows the Gaussian distribution of N (0, \(\sigma_{\rm j}\)) and the input is a sinusoidal signal of a frequency \(f_{\rm in}\) [32], [33].

\[\begin{eqnarray*} &&\!\!\!\!\! P_j=A^2\left[1-\exp\left(-2\pi^2 f_{in}^2 \sigma_j^2\right)\right] \tag{1} \\ &&\!\!\!\!\! \mathit{SNR}=-10\log 2\left[1-\exp \left(-2\pi^2 f_{in}^2 \sigma_j^2\right)\right] \quad \mbox{[dB]}. \tag{2} \end{eqnarray*}\]

It was impressive that the third author of [33] knew and used the following formulae (3), (4) for derivation of Eqs. (1), (2):

\[\begin{eqnarray*} &&\!\!\!\!\! E\left[\cos\left(\omega\varepsilon_n\right)\right]=\exp \left(-\frac{\omega^2\sigma_j^2}{2}\right) \tag{3} \\ &&\!\!\!\!\! E\left[\sin\left(\omega\varepsilon_n\right)\right]=0. \tag{4} \end{eqnarray*}\]

Notice that in actual sampling circuit, jitter distribution is often not Gaussian.

It is widely believed that sampling jitter effect is the fundamental limitation of the ADC performance. But the author considers that the continuous-time \(\Delta\Sigma\) ADC can overcome this problem; jitter effects for internal ADC are noise-shaped and those for internal DAC can be reduced by jitter insensitive DAC design (such as RF DAC) [34], [35].

Our jitter measurement circuit and jitter reduction circuit are shown in Figs. 11, 12 respectively [36]-[38], developed by their first author.

Fig. 11  Jitter measurement circuit [36] ©IEEE.

Fig. 12  Conceptual image of the proposed clock jitter reduction circuit using a phase averaging between uncorrelated self-delayed clock edges [38].

Further we investigated input-dependent sampling-time error effects in MOS samplers [39] and finite aperture time affects in sampling circuit (Fig. 13) [40] as well as timing error effects for DAC [41] and CMOS ADC nonlinear input capacitance for input differential amplifier array [42]; these were done to understand the AMS circuits and systems well.

Fig. 13  Sampling circuit with aperture time \(\tau\) [40] ©IEEE.

4.  Nyquist-Rate DAC

4.1  Relaxation DAC with HPF

The author considers that differentiation or high-pass filter is interesting. Also, he taught two’s complement in his basic circuit course. Then he came up with HPF usage for a relaxation DAC (ReDAC) (Fig. 14) and found that it produces with positive and negative polarity output for digital input in two’s complement format [43]. The proposed ReDAC with HPF is an extension of the original ReDAC using LPF which generates an analog output with only positive polarity.

Fig. 14  Relaxation DAC with HPF [43].

4.2  Gray-Code Input DAC

When the author started to study ADC design, he realized that Gray-code is frequently used there because it is robust compared to the binary code. Gray code is a binary numeral system where two successive values differ in only one bit, and the conversion between binary-code and Gray-code can be easily realized by XOR circuits (Table 1).

Table 1  Binary code and Gray code.

Then he wondered why it is not used for DAC; if it is used, the glitch can be reduced. DAC glitch is a serious problem such as in graphic display applications. He asked the authority of ADC/DAC design, who answered that the Gray-code input DAC configuration had not been invented even though many researchers tried.

The author taught at his circuit class that Gray code and binary code are converted using EXOR logic. Then his group came up with three types of Gray code input DACs (current-steering, charge-mode and voltage-mode DACs) which use analog switch matrices equivalent to EXOR (Fig. 15) [44].

Fig. 15  Gray-code input current-mode DAC [44] ©IEEE.

4.3  DAC Architectures Based on Number Theory

Integers have many interesting properties such as polygonal number theorem and Goldbach conjecture of prime numbers, and we considered to use these for new DAC architectures as curiosity-driven university research: polygonal number DAC and prime number DAC [45]. We showed that each consists of a few current sources, a resistor network, switch arrays and a decoder circuit. Properties of these DACs are positioned between binary and unary DAC ones.

4.4  DAC Linearity Improvement Algorithm with Unit Cell Sorting Based on Magic Square

The author enjoyed introductory mathematical books which describe about Magic Square (Fig. 16), Latin Square and Knight Tour. These were intellectually interesting but their effective applications were not found. Then he considered whether they can be applied to AMS IC design; this is curiosity-driven research. We proposed to use Magic Square, Latin Square and Euler Knight Tour as unit cell selection order algorithms of 2D pseudo random number sequences to cancel systematic mismatch effects among unit cells of a unary DAC and improve its linearity (Fig. 17) [46]-[48].

Fig. 16  \(4\times 4\) Magic square and its constant sum characteristics.

Fig. 17  Magic square layout of unit cells for a unary DAC which cancels their linear/quadratic gradient errors.

We also investigated an algorithm called 3-stage current sorting in half-unary weighted current cells to improve the linearity of a current-steering DAC [49].

4.5  Unit Cell Mismatch Scrambling Method for High-Resolution Unary DAC Based on Virtual 3D Layout

We proposed a unit cell mismatch scrambling method for a high-resolution unary DAC based on virtual 3D layout, to improve its Spurious Free Dynamic Range (SFDR) [50]. This can be implemented with simple interconnections and scrambling circuits, compared to that based on the 2D layout.

It is to care for the static characteristics mismatches using the Dynamic Element Matching (DEM) for the unary DAC. We consider here the signal bandwidth of the DAC is from DC to half of the sampling frequency or higher frequency, so that the DEM technique only needs to spread the spectrum of the spurious tones caused by the mismatches in the entire signal band uniformly without need for mismatch shaping; this is called as mismatch scrambling. However, direct implementation circuit of such mismatch scrambling for the high-resolution unary DAC becomes complicated. We investigated a more hardware efficient method by considering a virtual 3D case, considering X-, Y- and Z-decoders (Fig. 18).

Fig. 18  X, Y, Z-decoders and unit cells with virtual 3D layout for 6-bit unary DAC [50].

The author came up with this idea from magic cube (or 3D magic square) and an intuition that logic of binary-to-thermometer decoder circuit has some regularity.

5.  Successive Approximation Register Analog-to-Digital Converter (SAR ADC)

We considered that some redundancy of the SAR ADC (Fig. 19) can relax the requirements for its internal component requirements; there the error is corrected digitally without its measurement. Then the overall performance of the circuit can be improved. The redundancy can be classified into two categories:

Fig. 19  SAR ADC configuration [51].

(i) Operation redundancy (temporal redundancy): If operation, such as number of SAR steps has some redundancy, the overall AD conversion time can be reduced as well as its reliability is improved.

(ii) Circuit redundancy (spatial redundancy): If redundant hardware, such as multiple SAR comparators is used in an SAR ADC, its overall conversion time can be smaller.

We have investigated both of them. It would be interesting that quantum computer needs redundancy and error correction.

5.1  General SAR ADC Algorithm with Operation Redundancy and Digital Error Correction

We generalized the algorithm for SAR ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling and sample-hold circuit incomplete settling) to be digitally corrected [51]. We generalized this non-binary search algorithm, and clarified which decision errors can be digitally correct. The algorithm requires more SAR ADC conversion steps than a binary search algorithm, but the sampling speed of an SAR ADC using this algorithm can be faster than that of a binary-search SAR ADC; this is because the latter must wait for the settling time of the DAC and the sample-hold circuit inside the SAR ADC.

5.2  Fibonacci-Sequence Weighted SAR ADC

The author learned from an introductory number theory book that a Fibonacci sequence has many interesting properties and even now new ones are being found. It is widely applied successfully to many areas. Then we considered to apply it to an operation redundancy SAR ADC algorithm. The Fibonacci sequence is defined as follows:

Fibonacci sequence weighted SAR approximates the redundant SAR ADC of the radix 1.6 with integer weights, using digital error correction (Fig. 20). Then we found that it is well balanced and fast operation configuration when the settling time of the internal DAC is taken care of. The beautiful characteristics of its “error correction range” were shown. Also, several related results were found [52], [53].

Fig. 20  Fibonacci-sequence weighed SAR ADC.

5.3  Fibonacci Sequence Weighted SAR ADC as Fibonacci Section Search

The author learned the Fibonacci section search algorithm (Fig. 21) and had an intuition that this is related to the Fibonacci sequence weighted SAR ADC. The Fibonacci section search algorithm is used for finding effectively the extreme value of the unimodal function. Then we found the equivalence between the Fibonacci sequence weighted SAR ADC and the SAR ADC based on the Fibonacci section search algorithm using the unimodal function obtained by the absolute value of the difference between the ADC input voltage and the internal DAC output [54].

Fig. 21  Explanation of Fibonacci section search (\(F\)k: \(k\)-th Fibonacci number) [54] ©IEEE.

5.4  Fibonacci Sequence Weighted DAC

We came up with also Fibonacci sequence weighted DAC using R-R resistor networks (Fig. 22) [55]; their termination resistors are important. This can be used inside the Fibonacci sequence weighted SAR ADC.

Fig. 22  Fibonacci-sequence weighted DAC [55] ©IEEE.

5.5  Pseudo Silver Ratio Weighted SAR ADC

It is well known that when the binary number is 1-bit left-shifted, it is equivalent to multiplication by 2. It is interesting that when it is represented with radix of \(\sqrt{2}\), 2-bit left-shift is equivalent to multiplication by 2 and 1-bit left-shift is to multiplication by \(\sqrt{2}\).

The sliver ratio (\(\sqrt{2}\)) is popular especially in Japanese cultures and one of the students considered the (pseudo) silver ratio weighted SAR ADC and found: this method can realize high speed SAR AD conversion when taking account into the internal DAC incomplete settling and using two internal clocks of different periods [56].

Notice that the pseudo silver ratio SA weights are given by

\[1, 1, 1, 2, 2, 4, 4, 8, 8, 16, 16, 32, 32, 64, 64, 128, 128, \ldots,\]

while the binary ones are

\[1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, \ldots\]

5.6  Binary SAR ADC with Three Comparators and Digital Error Correction

One of research associates invented an SAR ADC algorithm using three comparators operating in parallel, instead of just one as in conventional SAR ADCs (Fig. 23) [57]-[59]; this is classified into the circuit redundancy SAR ADC. This comparator redundancy enables higher resolution, potentially faster operation, higher reliability and comparator-error correction. We investigated and derived its error-correction algorithm.

Fig. 23  SAR ADC with three comparators [57].

5.7  Non-Binary SAR ADC Algorithm with Two or Three Comparators

We investigated the design method of an SAR ADC with redundant circuit (two or three comparators) and redundant number of steps, together with digital error correction [60], [61]. Their error correction ranges were clarified. This is the generalization of our previous SAR ADC with 3 comparators but without step redundancy and the one with redundant number of steps using one comparator.

5.8  Design for Testability That Reduces Linearity Testing Time of SAR ADCs

We developed an SAR ADC chip whose SA weights and number of steps are programmable [62]. As its application we came up with design-for-testability (DFT) of SAR ADC that significantly reduces the testing time of its DC linearity with the ramp input signal (Fig. 24). There are only a limited number of successful ADC DFTs, and this is our trial.

Fig. 24  Operation of SAR ADC with DFT; number of SA steps can be reduced from 4 to 2 in DC linearity test mode by preadjusting the reference voltage corresponding to the known value of the analog input Vin [62].

Remarks:

1. Other testing related technologies of the SAR ADC with redundancy are discussed in [63], [64].
2. Non-binary two-comparator charge-sharing SAR ADC with digital compensation for comparator offset effects is shown in [65].
3. We should notice that single-comparator SAR ADC with operation redundancy increases the number of steps so that the dynamic power consumption increases compared to the binary one without redundancy.

6.  Time-Interleaved ADC

6.1  Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems

The author was involved in an ultra-high-speed ADC research project and reviewed several related papers in Hewlett Packard Journals; one of them was about time-interleaved ADC issues, which inspired him a lot.

A time-interleaved ADC system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits (Fig. 25). In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. However, mismatches such as offset, gain, bandwidth mismatches among channel ADCs as well as timing skew of the clocks distributed to them degrade SNDR of the ADC system as a whole. We analyzed their effects in time and frequency domains [66].

Fig. 25  Time-interleaved ADC [66] ©IEEE.

Remarks:

1. Linearity mismatch issues are described in [67], [68].
2. Notice that the time-interleaved ADC architecture is used for low-power in consumer electronics as well as high-speed-sampling in measurement instruments.
3. We investigated a bandwidth-interleaved DAC [69].
4. We learned that multi-path (such as time-interleaved, bandwidth interleaved and I, Q-path) and multi sampling clocks in AMS circuits have mismatch problems.

6.2  Digital Compensation Method for Timing Mismatches in Time-Interleaved ADC

The most serious mismatch effect for a wideband time-interleaved ADC is the timing skew among channel ADCs. Many compensation methods for it have been proposed which have their own advantages and disadvantages. We targeted for ATE system applications and there its digital calibration is desirable instead of analog one. Then we came up with combining correlation method and fine-delay digital filter for its calibration (Fig. 26) [70].

Fig. 26  Cross-correlation for timing skew detection in two-channel interleaved ADC [70] ©IEEE.

We use cross-correlation among channel ADC outputs to detect channel timing skew, and do successive-approximation timing adjustments using our proposed linear-phase-digital delay filter to compensate for the timing skew. It was found that using multi-tone input signals with cross-correlation of outputs provided a more robust way of detecting timing skew than using a single tone.

6.3  Digital Filter for Fine Time Delay

We came up with the idea of an FIR digital filter for fine time delay adjustment, by considering the sinc function sampling in time domain (Fig. 27). Our digital filter can set its group delay with the arbitrary fine time resolution while it maintains the linear phase characteristics [71], [72]; this can be used such as for the timing skew adjustment of the time-interleaved ADC sampling clocks described above.

Fig. 27  Sampling timing shift can maintain the linear phase characteristics. Impulse response, and gain, phase [71] ©IEEE.

7.  Time-to-Digital Converter (TDC)

Time domain analog circuits such as TDCs are now popular at international conferences in AMS circuit and system area. However, notice that handling the circuit dynamics (timing, bandwidth, slew-rate) is often difficult and troublesome, compared to the voltage signal handling circuit. Also notice that TDCs have been used especially in ATE systems for timing measurement in practice.

7.1  SAR TDC with Trigger Circuit

There are many interesting analog circuits for electronic measurement instruments. A long time ago, Tektronix presented a paper about the trigger circuit in an oscilloscope in an international conference on measurement technologies (Fig. 28). Then later, a TDC became popular and the author came up with its application to an SAR TDC (Fig. 29).

Fig. 28  Trigger circuit [73] ©IEEE.

Fig. 29  SAR TDC with trigger circuits [73] ©IEEE.

Using the trigger circuits, the rising-edge timing difference between two input timing signals can be held. This enables the SAR TDC to measure the timing when two timing inputs are single-shot as well as repetitive two clocks [73].

It was pointed out at an international conference that an oscillator consumes some amount of power. However, for multi-channel usage of TDCs, it can be shared among them.

7.2  Integral-Type TDC

We came up with an integral-type TDC, inspired by an integral-type ADC (Fig. 30) [74]. It can achieve fine time measurement resolution as its measurement time becomes longer and it does not need delay lines. It employs two counters and a repetitive timing signal with a stable frequency clock as well as external reference sine and cosine signals. The input timing difference is measured by a statistical Monte Carlo method.

Fig. 30  Integral-type TDC with trigger circuits [74] ©IEEE.

We found that the golden-ratio relationship between the reference sine/cosine signal frequency and the sampling clock frequency is desirable [75], [76].

7.3  TDC Using Two Oscillators with Different Frequencies

As modification of the integral-type TDC, we came up with TDC architectures using two asynchronous oscillators with different frequencies [76]; each starts oscillation with different frequencies from the rising timing of the corresponding input timing signal. By counting their oscillation start phase difference using digital counters, a highly linear stable TDC can be realized.

We came up with two architectures using this principle: analog centric one and digital centric one. The analog centric one uses oscilloscope trigger circuits and the digital centric one uses ring oscillators. For analog centric one, its operation is stable but two external asynchronous sine signals are required (Fig. 31). For digital centric one, all TDC circuits including the calibration can be implemented with full digital circuit.

Fig. 31  Analog centric TDC using two oscillators with different frequencies [76] ©IEEE.

7.4  Residue Arithmetic TDC and Gray Code TDC

We came up with a TDC architecture with residue arithmetic architecture from the motivation of applying the number theory to the AMS circuit design [77]. It can reduce the hardware and power significantly compared to a flash type TDC while keeping comparable performance. But later it was found that it generates a glitch.

Then we came up with a glitch-free TDC based on Gray code, which is an improved version of the residue arithmetic TDC (Fig. 32) [78]. It also keeps advantages of the residue arithmetic TDC.

Fig. 32  Gray-code TDC architecture in 6-bit case [78] ©IEEE.

7.5  Stochastic TDC Architecture

Proactive use of variations leads to fine time resolution TDC with full digital circuit was investigated. The author had some knowledge of both the TDC linearity self-calibration with the histogram method and the stochastic TDC. Then he came up with combining them (Fig. 33), and the invented TDC architecture has the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit with the histogram method for linearity improvement. (3) Stochastic architecture for fine time resolution with proactive use of MOSFET characteristics and routing variations [79]-[81].

Fig. 33  Stochastic TDC with linearity self-calibration [79] ©IEEE.

7.6  TDC Linearity Calibration with Metallic Ratio Equivalent-Time Sampling

We implemented a linearity self-calibration TDC with the histogram method using an analog FPGA. This is a foreground calibration, where the normal operation is stopped, the circuit itself measures its own error and then it is compensated by the circuit itself. We performed its experiment, but its linearity accuracy was saturated even if a long calibration time was taken. At that time, its reason was not clear. Later we came up with usage of the metallic ratio sampling, which was successful [82].

7.7  ADC Architecture Using TDC

The first author in [83] developed an ADC architecture using TDC for ATE applications (Fig. 34). Since a flash-type TDC is realized with full digital circuits, this ADC can be implemented with mostly digital circuits, which is suitable for fine CMOS implementation. In other words, this ADC performance becomes better as the CMOS technology becomes advanced even though the supply voltage is reduced. This demonstrated that time domain analog signal processing is suitable for fine CMOS technology.

Fig. 34  Time-domain ADC architecture and its operation. It employs a TDC and performs non-uniform sampling [83].

Also note that this ADC performs non-uniform sampling because the sampling timing depends on the input voltage value, and digital signal processing to convert non-uniform sampling data to uniform one is required.

8.  \(\Delta\Sigma\) ADC, DAC, TDC and DC-DC Converter

The author has a strong belief that \(\Delta\Sigma\) techniques are applicable to many fields, which always lead to success.

8.1  Complex Bandpass \(\Delta\Sigma\)AD Modulator Without I, Q-Path Crossing Layout and Complex BP DWA Algorithm

We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass \(\Delta\Sigma\)AD modulator which had our new architecture and algorithm [84], [85]. We came up with a complex bandpass filter structure in the forward path with I, Q dynamic matching for the reduction of mismatches between I and Q paths (Fig. 35) [86]. Also we came up with a complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy (Fig. 36) [87]. The chip employed both of them to evaluate their effectiveness.

Fig. 35  Architecture of our complex bandpass \(\Delta\Sigma\)AD modulator [86].

Fig. 36  Explanation of our complex bandpass DWA algorithm. The unit current cells in the ON state are filled in red for a real part (I-path) and in blue for an imaginary part (Q-path), when the complex input data are sequentially given by 4+3j, 2+5j, 3+j, 6+2j, …[87].

8.2  Limit Cycle Suppression Technique Using Digital Dither in \(\Delta\Sigma\) DA Modulator

We came up with a digital dither technique to suppress limit cycles in a \(\Delta\Sigma\) DA modulator [88]. It uses an XOR gate at the modulator output and the digital dither is generated by another \(\Delta\Sigma\)D modulator. The resolution of the DAC following the modulator is 1-bit (instead of multi-bit) thanks to XOR gate usage, and the overall SNDR does not degrade because the dither is added at the output and hence it is noise-shaped (Fig. 37). Notice that limit cycles are usually not observed in in a \(\Delta\Sigma\) AD modulator due to the device noise inside the AD modulator.

Fig. 37  \(\Delta\Sigma\) DA modulator with digital dither [88].

8.3  Phase Noise Measurement Techniques Using \(\Delta\Sigma\) TDC

It was demanded from industry that short-time testing of phase noise without spectrum analyzer is required at mass-production shipping stage.

Then we came up with a technique for measuring phase noise of a clock using a \(\Delta\Sigma\) TDC (Fig. 38) [89]. It can be implemented with simple circuitry, due to the following: (i) Clock under test (CUT) is a repetitive signal. (ii) Time resolution with CUT and reference clock can be finer by using longer measurement time with the \(\Delta\Sigma\) TDC. (iii) Phase noise power spectrum can be calculated from the \(\Delta\Sigma\) TDC output data using FFT.

Fig. 38  \(\Delta\Sigma\) TDC configuration [89] ©IEEE.

8.4  Band-Select Noise Spread Spectrum Clocking

We investigated a \(\Delta\Sigma\) TDC and then as its duality, one of students simulated a \(\Delta\Sigma\) digital-time converter (DTC). We observed its simulation results in frequency domain and came up with usage as band-select spread spectrum clock for DC-DC converters [90]. This technique can exclude the noise spectrum spread such as in AM, FM radio bands (Fig. 39). Later its several extensions have been investigated by leading of a visiting professor of Gunma University [91].

Fig. 39  Band-select spectrum spread [90].

9.  Dynamic Element Matching Technologies

It was pointed out by an industry researcher that “multi-bit” usage is mandatory for low-power \(\Delta\Sigma\)AD modulator, because the operational amplifier slew-rate requirement is significantly relaxed. However, the multi-bit DAC has some nonlinearities in the feedback path, which degrade the overall SNDR of the \(\Delta\Sigma\) ADC if no care is taken. Then we investigated several digital signal processing algorithms to suppress the multi-bit DAC nonlinearity effects, which is one of the digitally-assisted analog technologies.

We developed various DWA algorithms:

Muti-BP \(\Delta\Sigma\) ADC DWA algorithms [92], Second-order LP DWA algorithms [93], [94], Complex single-BP DWA algorithm [87], Complex multi-BP DWA algorithms [95], DWA algorithms for BP \(\Delta\Sigma\) DAC with ternary unit cells [96], DWA and self-calibration algorithms of multi-bit \(\Delta\Sigma\) TDC [97], [98].

Here are some comments:

(i) The DWA algorithm with 1^st-order noise-shaping of DAC nonlinearities can be implemented with simple hardware, whereas the one for the second-order is complicated; this is valid for all DWA algorithms of the second-order reported up-to now.

(ii) Two DACs are used in a complex BP modulator and its DWA algorithm utilizes cross-coupled order selection of unit cells in two DACs (Fig. 35) [87], [95].

(iii) As far as we know, we are the first for development of the multi-bit \(\Delta\Sigma\) TDC DWA algorithm [97], [98].

(iv) To our knowledge, there is no systematic method for development of DWA algorithms [99].

(v) Dynamic matching technique can be also applied to a I, Q-path of a transmitter circuit [100].

10.  Other Circuits

10.1  Folding/Interpolation ADC and Digital Error Correction Algorithm

The author was involved in the development of a high-speed 6-bit ADC using SiGe Hetero-Junction Bipolar Transistor (HBT) for measuring instrument applications [101]. The folding/interpolation architecture is suitable for ADC design with HBT, which employs an analog encoding signal processing.

We also investigated its digital error correction algorithms by finding out very small redundancy [102]. The relationships between error correction and input signal frequency were clarified. The lower bits obtained by the interpolation circuit with redundancy correct the higher bits by the folding circuits.

Later the author realized that this is common for many digital error correction algorithms of various ADCs and that this is similar to a digital adder where lower bits are calculated first and their generated carries are propagated to higher bits.

10.2  Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme

We investigated ADC self-calibration technologies due to the industry demand. The background calibration uses indirect error measurements and an adaptive signal processing algorithm; it is performed during normal operation time. In other words, no calibration time slot is required. All of these operations are done by the circuit itself without help of the circuit user outside.

As one of them we investigated a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a split ADC structure [103]. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed (Fig. 40). However, the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration. We investigated the split ADC structure for its background calibration with fast convergence.

Fig. 40  Pipeline ADC using open-loop amplifier [103].

10.3  Analysis and Design of Operational Amplifier Stability Based on Routh-Hurwitz Stability Criterion

Control theory is basis of analog circuit design. Bode chart based on Nyquist stability criterion is widely used for operational amplifier design. But the author wondered why Routh-Hurwitz stability criterion was not used in circuit design, and finally realized that many of AMS circuit designers did not know it correctly; this fact was very surprising to the author.

Then we investigated to use Routh-Hurwitz stability criterion in addition to Nyquist one for analysis and design of the operational amplifier stability, when its small equivalent circuit is derived; this can lead to explicit stability condition derivation for operational amplifier circuit parameters, and this is effective especially for multi-stage operational amplifiers [104].

10.4  MOS Reference Current Source

During the author’s lecture about CMOS analog circuit to his laboratory members, he assigned several modifications of current sources and one of students showed her simulation results, which was the design improvement of the constant current source (peaking current mirror), originally invented by Nagata Minoru in 1966 (Fig. 41(a)).

Also, several researchers in industry suggested MOS drain current temperature characteristics with respect to the gate voltage (Fig. 41(b)).

Fig. 41  Investigated MOS reference current source [108] ©IEEE.

We applied these to MOS reference current source circuits insensitive to supply voltage and temperature [105]-[108]. These demonstrated that there are still analog circuit design challenges with a small number of MOS transistors.

10.5  AMS Circuit and System Testing Technologies

AMS circuit and system testing technologies are important but their researchers are not so many in universities. Then we have been engaged in the research for them by collaborating with industry [109]-[124]. These are at the boundary between AMS circuit and LSI testing technologies. Also, Physically Unclonable Function (PUF) has been investigated by applying the TDC linearity self-calibration method [125].

10.6  DC-AC Conversion Technique for Very Small DC Voltage

The author experienced two industry-collaboration research projects with two different companies independently. Both are for very small DC voltage measurement; one is that for analog IC related small voltage/current with DC-AC conversion (Fig. 42) [122]-[124] and the other is that for strain measurement using strain gauge (Fig. 43) [126]. Both research associates used the DC-AC conversion technique and both were successful. We recognized that in general this technique is useful for very small DC voltage measurement with high accuracy by suppressing the low-frequency noise effects.

Fig. 42  DC-AC conversion circuit [124] ©IEEE.

Fig. 43  Bridge circuit with strain gauge [126].

10.7  Power Electronics Circuits

We consider that power electronics circuits play an important role worldwide, and we have been engaged in their study with our research associates: DC-DC converter [127]-[130], EMI reduction [131], [132], charge pump circuit [133]-[135], measurement technique [136], energy harvest [137], envelope tracking power supply (Fig. 44) [138], coupled inductor analysis (Fig. 45) [139], digital PWM generator [140] and IGBT gate driver [141].

Fig. 44  Envelope tracking power supply circuit [138] ©IEEE.

Fig. 45  Two-phase coupled-inductor buck converter [139].

10.8  Floating-Point Digital Arithmetic Circuit Based on Taylor-Series Expansion

The author realized that Taylor-series expansion has its conversion region; for some functions, it is very wide while for others, it is limited. Then we considered to apply it to some floating-point digital arithmetic circuits for good tradeoff among memory size, required numbers of additions/subtractions/multiplications, and computing accuracy [142], [143].

10.9  Research Results Led by Research Associates

There are also some research results led by visiting professors and researchers as well as Ph.D. course students in the author’s lab: device modeling [144]-[147], laterally diffused MOS (LDMOS) device [148]-[150], analog filter [151]-[154], sensor [155], neural network [156], wireless power transmission [157], computer fluid dynamics [158] and distancing-free mask [159], [160].

11.  Conclusion

This paper has reviewed the author’s group research achievements in AMS circuit and system area with the introduction of thinking way and research motivation. Thanks to many excellent research collaborators and students, they cover wide range of areas such as algorithms, circuits, systems, modeling, devices, and testing. Since some of them are algorithm-oriented and technology-independent, hopefully they can live a long time in digital exploding society. This paper is closed by remarking that teaching students at classes as well as discussions with researchers are very helpful for new ideas.

Acknowledgments

The author would like to thank all of his group members and research associates who have contributed the research mentioned in this paper. This work was supported by JSPS KAKENHI Grant Number 21K04190 and 21KK0080.

References

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[62] T. Ogawa, H. Kobayashi, S. Uemori, Y. Tan, S. Ito, N. Takai, T.J. Yamaguchi, and K. Niitsu, “Design for testability that reduces linearity testing time of SAR ADCs,” IEICE Trans. Electron., vol.E94-C, no.6, pp.1061-1064, June 2011.

[63] T. Ogawa, H. Kobayashi, Y. Tan, S. Ito, S. Uemori, N. Takai, K. Niitsu, T.J. Yamaguchi, T. Matsuura, and N. Ishikawa, “SAR ADC that is configurable to optimize yield,” IEEE Asia Pacific Conference on Circuits and Systems, Dec. 2010.

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[69] N. Ishida, K. Asami, S. Katayama, A. Kuwana, and H. Kobayashi, “Frequency interleaved DAC system design: Fundamental problems and compensation methods,” Proc. 8th International Congress on Information and Communication Technology, Lecture Notes in Networks and Systems, vol.694, Springer, Aug. 2023.

[70] R. Yi, M. Wu, K. Asami, H. Kobayashi, R. Khatami, A. Katayama, I. Shimizu, and K. Katoh, “Digital compensation for timing mismatches in interleaved ADCs,” IEEE Asian Test Symposium, Nov. 2013.

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[74] Y. Sasaki and H. Kobayashi, “Integral-type time-to-digital converter,” IEEE International Conference on Solid-State and Integrated Circuit Technology, Nov. 2018.

[75] H. Kobayashi, K. Machida, Y. Sasaki, Y. Osawa, P. Zhang, L. Sha, Y. Ozawa, and A. Kuwana, “Fine time resolution TDC architectures-integral and delta-sigma types,” IEEE International Conference on ASIC, Oct. 2019.

[76] K. Machida, U. Ozawa, Y. Abe, and H. Kobayashi, “Time-to-digital converter architectures using two oscillators with different frequencies,” IEEE Asian Test Symposium, Oct. 2018.

[77] C. Li, K. Katoh, J. Wang, S. Wu, S.N. Mohyar, and H. Kobayashi, “Time-to-digital converter architecture with residue arithmetic and its FPGA implementation,” International SoC Design Conference, Nov. 2014.

[78] C. Li and H. Kobayashi, “A glitch-free time-to-digital converter architecture based on gray code,” IEEJ Trans. EIS, vol.136, no.1, pp.22-27, Jan. 2016.

[79] S. Ito, S. Nishimura, H. Kobayashi, S. Uemori, Y. Tan, N. Takai, T.J. Yamaguchi, and K. Niitsu, “Stochastic TDC architecture with self-calibration,” IEEE Asia Pacific Conference on Circuits and Systems, Dec. 2010.

[80] C. Li, J. Wang, H. Kobayashi, and R. Shiota, “Stochastic TDC architecture with self-calibration and its RTL verification,” IEEJ Trans. EIS, vol.137, no.2, pp.335-341, Feb. 2017.

[81] K. Katoh, Y. Kobayashi, T. Chujo, J. Wang, E. Li, C. Li, and H. Kobayashi, “A small chip area stochastic calibration for TDC using ring oscillator,” J. Electron. Test., vol.30, no.6, pp.653-663, Springer, Dec. 2014.

[82] S. Yamamoto, Y. Sasaki, Y. Zhao, A. Kuwana, K. Katoh, Z. Zhang, J. Wei, T.M. Tran, S. Katayama, K. Sato, T. Ishida, T. Okamoto, T. Ichikawa, T. Nakatani, K. Hatayama, and H. Kobayashi, “Metallic ratio equivalent-time sampling and application to TDC linearity calibration,” IEEE Trans. Device Mater. Rel., vol.22, no.2, pp.142-153, June 2022.

[83] T. Komuro, et al., “ADC architecture using time-to-digital converter,” IEICE Trans. Electron. (Japanese Edition), vol.J90-C, no.2, pp.125-133, Feb. 2007.

[84] H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, T. Matsuura, K. Yahagi, J. Kudoh, H. Nakane, M. Hotta, T. Tsukada, K. Mashiko, and A. Wada, “A second-order multi-bit complex bandpass ΔΣAD modulator with I, Q dynamic matching and DWA algorithm,” IEICE Trans. Electron., vol.E90-C, no.6, pp.1181-1188, June 2007.

[85] H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, J. Kudoh, K. Yahagi, T. Matsuura, H. Nakane, H. Kobayashi, M. Hotta, T. Tsukada, K. Mashiko, and A. Wada, “A multibit complex bandpass ΔΣAD modulator with I, Q dynamic matching and DWA algorithm,” IEEE Asian Solid-State Circuits Conference, Nov. 2006,

[86] H. San, A. Hayakawa, Y. Jingu, H. Wada, H. Hagiwara, K. Kobayashi, H. Kobayashi, T. Matsuura, K. Yahagi, J. Kudoh, H. Nakane, M. Hotta, T. Tsukada, K. Mashiko, and A. Wada, “Complex bandpass ΔΣAD modulator architecture without I, Q-path crossing layout,” IEICE Trans. Fundamentals, E89-A, no.4, pp.908-915, April 2006.

[87] H. San, et al., “A noise-shaping algorithm of multi-bit DAC nonlinearities in complex bandpass ΔΣAD modulators,” IEICE Trans. Fundamentals, E87-A, no.4, pp.792-800, April 2004.

[88] J. Kojima, Y. Arai, and H. Kobayashi, “Study on ΔΣ DA modulator performance improvement using digital dither,” IEEJ Trans. EIS, vol.136, no.12, pp.1767-1772, Dec. 2016.

[89] Y. Osawa, D. Hirabayashi, N. Harigai, H. Kobayashi, K. Niitsu, and O. Kobayashi, “Phase noise measurement techniques using delta-sigma TDC,” IEEE International Mixed-Signals, Sensors and Systems Test Workshop, Sept. 2014.

[90] R. Khatami, et al., “ΔΣ digital-to-time converter and its application to SSCG,” IEICE International Conference on Integrated Circuits Design and Verification, Nov. 2013.

[91] Y. Sun, Y. Kobori, A. Kuwana, and H. Kobayashi, “Pulse coding controlled switching converter that generates notch frequency to suit noise spectrum,” IEICE Trans. Commun., vol.E103-B, no.11, pp.1331-1340, Nov. 2020.

[92] A. Motozawa, et al., “Multi-band-pass ΔΣ modulator techniques and their applications,” IEICE Trans. Electron. (Japanese Edition), vol.J90-C, no.2, pp.143-158, Feb. 2007.

[93] H. Hagiwara, et al. “DA converter circuits provided with DA converter of segment switched capacitor type,” Patent Application no.: 11/157,923 (U.S.), Application Date: June 22, 2005.

[94] H. Hagiwara, et al., “A second-order DWA algorithm for multi-bit lowpass ΔΣAD modulators,” IEEJ Electronic Circuit Workshop, June 2004.

[95] M. Murakami, H. Kobayashi, S.N.B. Mohyar, O. Kobayashi, T. Miki, and J. Kojima, “I-Q signal generation techniques for communication IC testing and ATE systems,” IEEE International Test Conference, Nov. 2016.

[96] J. Kojima, N. Kushita, M. Murakami, A. Kuwana, and H. Kobayashi, “DWA algorithm for band-pass ΔΣ DAC with ternary unit cells,” IEEE International Conference on Solid-State and Integrated Circuit Technology, Nov. 2018.

[97] S. Uemori, M. Ishii, H. Kobayashi, D. Hirabayashi, Y. Arakawa, Y. Doi, O. Kobayashi, T. Matsuura, K. Niitsu, Y. Yano, T. Gake, T.J. Yamaguchi, and N. Takai, “Multi-bit sigma-delta TDC architecture with improved linearity,” J. Electron. Test., vol.29, no.6, pp.879-892, Dec. 2013.

[98] T. Chujo, D. Hirabayashi, T. Arafune, S. Shibuya, S. Sasaki, H. Kobayashi, M. Tsuji, R. Shiota, M. Watanabe, N. Dobashi, S. Umeda, H. Nakamura, and K. Sato, “Timing measurement BOST with multi-bit ΔΣ TDC,” IEEE International Mixed-Signal Testing Workshop, June 2015.

[99] H. Kobayashi, J.-L. Wei, M. Murakami, J.-Y. Kojima, N. Kushita, Y. Du, and J. Wang, “Performance improvement of delta-sigma ADC/DAC/TDC using digital technique,” IEEE International Conference on Solid-State and Integrated Circuit Technology, Nov. 2018.

[100] J. Otsuki, H. San, H. Kobayashi, T. Komuro, Y. Yamada, and A. Liu, “Reducing spurious output of balanced modulators by dynamic matching of I, Q quadrature paths,” IEICE Trans. Electron., vol.E88-C, no.6, pp.1290-1294, June 2005.

[101] H. Kobayashi, et al., “A high-speed 6-bit ADC using SiGe HBT,” IEICE Trans. Fundamentals, vol.E81-A, no.3, pp.389-397, March 1998.

[102] H. Kobayashi, H. Sakayori, T. Tobari, and H. Matsuura, “Error correction algorithm for folding/interpolation ADC,” IEEE International Symposium on Circuits and Systems, May 1995.

[103] T. Yagi, K. Usui, T. Matsuura, S. Uemori, S. Ito, Y. Tan, and H. Kobayashi, “Background self-calibration algorithm for pipelined ADC using split ADC scheme,” IEICE Trans. Electron., vol.E94-C, no.7, pp.1233-1236, July 2011.

[104] J. Wang, G. Adhikari, N. Tsukiji, and H. Kobayashi, “Analysis and design of operational amplifier stability based on Routh-Hurwitz stability criterion,” IEEJ Trans. EIS, vol.138, no.12, pp.1517-1528, Dec. 2018.

[105] M. Hirano, N. Kushita, Y. Moroshima, H. Harakawa, T. Oikawa, N. Tsukiji, T. Ida, Y. Shibasaki, and H. Kobayashi, “Silicon verification of improved Nagata current mirrors,” IEEE International Conference on Solid-State and Integrated Circuit Technology, Nov. 2018.

[106] M. Hirano, N. Tsukiji, and H. Kobayashi, “Simple reference current source insensitive to power supply voltage variation ― Improved Minoru Nagata current source,” IEEE International Conference on Solid-State and Integrated Circuit Technology, Oct. 2016.

[107] T. Feng, H. Tanimoto, T. Kamio, S. Yamamoto, T. Hosono, S. Katayama, K. Ootomo, A. Kuwana, and H. Kobayashi, “A reference current source with cascaded Nagata current mirrors insensitive to supply voltage and temperature,” IEEE International Conference on Solid-State and Integrated Circuit Technology, Oct. 2022.

[108] T. Hosono, T. Kamio, S. Yamamoto, J. Matsuda, K. Hirai, S. Katayama, T. Feng, A. Kuwana, H. Kobayashi, A. Suzuki, S. Yamada, T. Kato, R. Kitakoga, T. Shimamura, G. Adhikari, N. Ono, and K. Miura, “CMOS Nagata current sources with self-bias configuration insensitive to supply voltage and temperature,” IEEE International Conference on Electrical, Computer and Energy Technologies, Dec. 2021.

[109] H. Kobayashi, A. Kuwana, J. Wei, Y. Zhao, S. Katayama, T.M. Tri, M. Hirai, T. Nakatani, K. Hatayama, K. Sato, T. Ishida, T. Okamoto, and T. Ichikawa, “Analog/mixed-signal circuit testing technologies in IoT era,” IEEE International Conference on Solid-State and Integrated Circuit Technology, Nov. 2020.

[110] H. Kobayashi, et al., “Analog/mixed-signal circuit testing technologies in IoT era,” IEEJ Trans. EIS, vol.141, no.1, pp.1-12, Jan. 2021.

[111] H. Kobayashi, “Signal generation technologies for analog/mixed-signal IC testing,” IEEE International Conference on ASIC, Oct. 2023.

[112] F. Abe, Y. Kobayashi, K. Sawada, K. Kato, O. Kobayashi, and H. Kobayashi, “Low-distortion signal generation for ADC testing,” IEEE International Test Conference, Oct. 2014.

[113] D. Iimori, T. Nakatani, S. Katayama, G. Ogihara, A. Hatta, A. Kuwana, K. Sato, T. Ishida, T. Okamoto, T. Ichikawa, J. Wei, Y. Zhao, T.M. Tran, K. Hatayama, and H. Kobayashi, “Summing node and false summing node methods: Accurate operational amplifier AC characteristics testing without audio analyzer,” IEEE International Test Conference, Oct. 2021.

[114] R. Aoki, K. Sato, T. Ishida, T. Okamoto, T. Ichikawa, S. Katayama, Y. Sasaki, K. Machida, T. Nakatani, J. Wang, A. Kuwana, K. Hatayama, and H. Kobayashi, “Evaluation of null method for operational amplifier short-time testing,” IEEE International Conference on ASIC, Oct. 2019.

[115] K. Sato, T. Nakatani, T. Ishida, T. Okamoto, T. Ichikawa, S. Katayama, D. Iimori, M. Takagi, Y. Zhao, S. Yamamoto, A. Kuwana, K. Katoh, K. Hatayama, and H. Kobayashi, “Low distortion sinusoidal signal generator with harmonics cancellation using two types of digital predistortion,” IEEE International Test Conference, Oct. 2023.

[116] K. Sato, T. Ishida, T. Okamoto, T. Ichikawa, J. Wei, T. Nakatani, Y. Zhao, S. Katayama, S. Yamamoto, A. Kuwana, K. Hatayama, and H. Kobayashi, “Revisit to accurate ADC testing with incoherent sampling using proper sinusoidal signal and sampling frequencies,” IEEE International Test Conference, Oct. 2021.

[117] K. Sato, T. Nakatani, S. Katayama, D. Iimori, G. Ogihara, T. Ishida, T. Okamoto, T. Ichikawa, Y. Zhao, K. Katoh, A. Kuwana, K. Hatayama, and H. Kobayashi, “High precision voltage measurement system utilizing low-end ATE resource and BOST,” IEEE Asian Test Symposium, Nov. 2022.

[118] P. Sarson, T. Yanagida, S. Shibuya, K. Machida, and H. Kobayashi, “A distortion shaping technique to equalize intermodulation distortion performance of interpolating arbitrary waveform generators in automated test equipment,” J. Electron. Test., vol.34, pp.215-232, June 2018.

[119] D. Iimori, et al., “SAR time-to-digital converter with 1 ps resolution for LSI test system,” International Congress on Information and Communication Technology, Lecture Notes in Networks and Systems, Springer, Feb. 2023.

[120] T. Komuro, N. Hayasaka, H. Kobayashi, and H. Sakayori, “A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI,” IEEE International Symposium on Circuits and Systems, May 2005.

[121] Y. Motoki, H. Sugawara, H. Kobayashi, T. Komuro, and H. Sakayori, “Multi-tone curve fitting algorithms for communication application ADC testing,” Electronics and Communication in Japan (Part II: Electronics), vol.86, no.8, pp.1-11, Feb. 2003.

[122] G. Ogihara, T. Nakatani, D. Iimori, S. Katayama, A. Kuwana, K. Sato, T. Ishida, T. Okamoto, T. Ichikawa, Y. Zhao, J. Wei, K. Hatayama, and H. Kobayashi, “Evaluation of high-precision nano-ampere current measurement method for mass production,” IEEE International Conference on Electronics Circuits and Systems, Nov. 2021.

[123] K. Sato, T. Nakatani, T. Ishida, T. Okamoto, T. Ichikawa, A. Kuwana, K. Hatayama, and H. Kobayashi, “Accurate testing of precision voltage reference by DC-AC conversion,” IEEE Asian Test Symposium, Nov. 2020.

[124] Y. Sasaki, T. Ichikawa, A. Kuwana, K. Hatayama, H. Kobayashi, K. Machida, R. Aoki, S. Katayama, T. Nakatani, J. Wang, K. Sato, T. Ishida, and T. Okamoto, “Accurate and fast testing technique of operational amplifier DC offset voltage in μV-order by DC-AC conversion,” IEEE International Test Conference in Asia, Sept. 2019.

[125] K. Katoh, S. Yamamoto, Z. Zhao, Y. Zhao, S. Katayama, A. Kuwana, T. Nakatani, K. Hatayama, H. Kobayashi, K. Sato, T. Ishida, T. Okamoto, and T. Ichikawa, “A physically unclonable function using time-to-digital converter with linearity self-calibration and its FPGA implementation,” IEEE International Test Conference in Asia, Sept. 2023.

[126] M. Kono, et al., “High-precision strain measurement bridge circuit with on-line compensation for parasitic capacitance effects,” IEICE Trans. Electron. (Japanese Edition), vol.J91-C, no.3, pp.204-216, March 2008.

[127] S. Wu, Y. Kobori, N. Tsukiji, and H. Kobayashi, “Transient response improvement of DC-DC buck converter by a slope adjustable triangular wave generator,” IEICE Trans. Commun., vol.E98-B, no.2, pp.288-295, Feb. 2015.

[128] M. Tran, Y. Sun, Y. Kobori, A. Kuwana, and H. Kobayashi, “Overshoot cancelation based on balanced charge-discharge time condition for buck converter in mobile applications,” IEEE International Conference on ASIC, Oct. 2019.

[129] Y. Sekine, S. Katayama, Y. Kobori, A. Kuwana, and H. Kobayashi, “Multi-output SEIPC multiplied boost converter with exclusive control,” IEEE International Conference on ASIC, Oct. 2021.

[130] Y. Kobori, F. Zhao, Q. Li, M. Li, S. Wu, Z. Nosker, S.N. Mohyar, N. Takai, H. Kobayashi, T. Odaguchi, I. Nakanishi, K. Ueda, and J. Matsuda, “Single inductor dual output switching converter using exclusive control method,” IEEE International Conference on Power Engineering, Energy and Electrical Devices, May 2013.

[131] T. Daimon, et al., “Spread-spectrum clocking in switching regulators for EMI reduction,” IEICE Trans. Fundamentals, vol.E86-A, no.2, pp.381-386, Feb. 2003.

[132] I. Mori, Y. Yamada, S.A. Wibowo, M. Kono, H. Kobayashi, Y. Fujimura, N. Takai, T. Sugiyama, I. Fukai, N. Onishi, I. Takeda, and J. Matsuda, “EMI reduction by spread-spectrum clocking in digitally-controlled DC-DC converters,” IEICE Trans. Fundamentals, vol.E92-A, no.4, pp.1004-1011, April 2009.

[133] T. Myono, et al., “Reducing startup-time inrush current in charge pump circuits,” IEICE Trans. Fundamentals, vol.E87-A, no.4, pp.787-791, April 2003.

[134] T. Myono, et al., “High-efficiency charge-pump circuits which use a 0.5 Vdd-step pumping method,” IEICE Trans. Fundamentals, vol.E86-A, no.2, pp.371-380, Feb. 2003.

[135] H. Sato and H. Kobayashi, “Dynamic power dissipation of track/hold circuit,” IEICE Trans. Fundamentals, vol.E83-A, no.8, pp.1728-1731, Aug. 2000.

[136] N. Tsukiji, Y. Kobori, and H. Kobayashi, “A study on loop gain measurement method using output impedance in DC-DC buck converter,” IEICE Trans. Commun., vol.E101-B, no.9, pp.1940-1948, Sept. 2018.

[137] Z. Nosker, Y. Kobori, H. Kobayashi, K. Niitsu, N. Takai, T. Oomori, T. Odaguchi, I. Nakanishi, K. Nemoto, and J. Matsuda, “A small, low power boost regulator optimized for energy harvesting applications,” Analog Integr. Circ. Sig. Process., vol.75, no.2, pp.207-216, April 2013.

[138] A. Kanbe, M. Kaneta, F. Yui, H. Kobayashi, N. Takai, T. Shimura, H. Hirata, and K. Yamagishi, “New architecture of envelope tracking power amplifier for base station,” IEEE Asia Pacific Conference on Circuits and Systems, Dec. 2008.

[139] S.A. Wibowo, Z. Ting, M. Kono, T. Taura, Y. Kobori, K. Onda, and H. Kobayashi, “Analysis of coupled inductors for low-ripple fast-response buck converter,” IEICE Trans. Fundamentals, vol.E92-A, no.2, pp.451-455, Feb. 2009.

[140] I. Mori, K. Kimura, Y. Yamada, H. Kobayashi, Y. Kobori, S.A. Wibowo, K. Shimizu, M. Kono, and H. San, “High-resolution DPWM generator for digitally controlled DC-DC converters,” IEEE Asia Pacific Conference on Circuits and Systems, Dec. 2008.

[141] S. Yamamoto, Y. Abe, A. Iwabuchi, J. Matsuda, A. Kuwana, H. Du, T. Kamio, T. Hosono, S. Katayama, and H. Kobayashi, “Current-driven IGBT gate driver circuit considering four operation regions,” International Congress on Information and Communication, Aug. 2022.

[142] J. Wei, A. Kuwana, H. Kobayashi, and K. Kubo, “IEEE754 Binary32 floating-point logarithmic algorithms based on Taylor-series expansion with mantissa region conversion and division,” IEICE Trans. Fundamentals, vol.E105-A, no.7, pp.1020-1027, July 2022.

[143] J. Wei, A. Kuwana, H. Kobayashi, K. Kubo, and Y. Tanaka, “Floating-point inverse square root algorithm based on Taylor-series expansion,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.68, no.7, pp.2640-2644, July 2021.

[144] H. Aoki and H. Kobayashi, “Self-heat characterizations and modeling of multi-finger n-MOSFETs for RF-CMOS applications,” IEEE Trans. Electron Devices, vol.62, no.9, pp.2704-2709, Sept. 2015.

[145] H. Aoki, N. Tsukiji, H. Sakairi, K. Chikamatsu, N. Kuroda, S. Shibuya, K. Kurihara, M. Higashino, H. Kobayashi, and K. Nakahara, “Electron mobility and self-heat modeling of AlN/GaN MIS-HEMTs with embedded source field-plate structures,” IEEE Compound Semiconductor Integrated Circuit Symposium, Oct. 2016.

[146] M. Higashino, H. Aoki, N. Tsukiji, M. Kazumi, T. Totsuka, S. Shibuya, K. Kurihara, and H. Kobayashi, “Study on ON-resistance degradation modeling used for HCI induced degradation characteristic of LDMOS transistors,” International Conference on Solid State Devices and Materials, Sept. 2016.

[147] Y. Arai, H. Aoki, F. Abe, S. Todoroki, R. Khatami, M. Kazumi, T. Totsuka, T. Wang, and H. Kobayashi, “Gate voltage dependent 1/f noise variance model based on physical noise generation mechanisms in n-channel metal-oxide-semiconductor field-effect transistors,” Jpn. J. Appl. Phys., vol.54, 04DC10 1-4, Feb. 2015.

[148] J. Matsuda, et al., “High reliability and low switching loss dual RESURF 40 V N-LDMOS transistor with grounded multi-step field plate,” Journal of Technology and Social Science, vol.7, no.1, pp.1-12, Jan. 2023.

[149] J. Matsuda, A. Kuwana, and H. Kobayashi, “Optimization of high reliability and wide SOA 100 V N-LDMOS transistor,” IEEJ Trans. EIS, vol.140, no.11, pp.1220-1229, Nov. 2020.

[150] J. Matsuda, A. Kuwana, J. Kojima, N. Tsukiji, and H. Kobayashi, “Wide SOA and high reliability 60-100 V LDMOS transistors with low switching loss and low specific on-resistance,” IEEE International Conference on Solid-State and Integrated Circuit Technology, Nov. 2018.

[151] T. Komuro, S. Sobukawa, H. Sakayori, M. Kono, and H. Kobayashi, “Total harmonic distortion measurement system for electronic devices up to 100 MHz with remarkable sensitivity,” IEEE Trans. Instrum. Meas., vol.56, no.6, pp.2360-2368, Dec. 2007.

[152] M. Takagi, T. Nakatani, S. Katayama, D. Iimori, G. Ogihara, Y. Zhao, A. Kuwana, K. Sato, T. Ishida, T. Okamoto, T. Ichikawa, K. Katoh, K. Hatayama, and H. Kobayashi, “Design consideration for LC analog filters: Inductor ESR compensation, mutual inductance effect and variable center frequency,” International Congress on Information and Communication Technology, Lecture Notes in Networks and Systems, vol.696, Aug. 2023.

[153] T.M. Tran, A. Kuwana, and H. Kobayashi, “Investigation of behaviors of Kerwin-Huelsman-Newcomb filters using Nichols charts of self-loop function,” IEEE International Midwest Symposium on Circuits and Systems, Aug. 2021.

[154] M.T. Tran, A. Kuwana, and H. Kobayashi, “Study of behaviors of multi-source rauch filters,” American Journal of Science & Engineering, vol.2, no.1, pp.35-52, April 2021.

[155] S. Wang, M.Z. Hossain, K. Shinozuka, N. Shimizu, S. Kitada, T. Suzuki, R. Ichige, A. Kuwana, and H. Kobayashi, “Graphene field-effect transistor biosensor for detection of biotin with ultra high sensitivity and specificity,” Biosensors and Bioelectronics, vol.165, 112363, Oct. 2020.

[156] M.M.H. Milu, M.A. Rahman, M.A. Rashid, A. Kuwana, and H. Kobayashi, “Improvement of classification accuracy of four-class voluntary-imagery fNIRS signals using convolutional neural network,” Eng. Technol. Appl. Sci. Res., vol.13, no.2, pp.10425-10431, April 2023.

[157] T. Yanagida, K. Machida, K. Asami, Y. Endo, and H. Kobayashi, “Harmonic suppression technique of magnetic field coupling type wireless power transmission system using ATAC circuit,” IEEE 14th International Conference on Solid-State and Integrated Circuit Technology, Nov. 2018.

[158] A. Kuwana, X.Y. Bai, D. Yao, and H. Kobayashi, “Numerical simulation for the starting characteristics of a wind turbine,” Advanced Engineering Forum, vol.38, pp.215-221, Nov. 2020.

[159] R.M. Galindo, et al., “Low-cost powered air-purifying respirator (PAPR) “Distancing-free mask frontline (DFM-F) prototype no.1” for the operational tests in hospitals in Cebu city, Philippines,” Mechanical and Electrical Intelligent System, vol.5, no.2, pp.1-6, April 2022.

[160] E. Carcasona, et al., “Very-low-cost powered air-purifying respirator (PAPR) “Distancing-free mask industry (DFM-I) prototype no.1” and proposal for a lockdown-free industry,” Journal of Technology and Social Science, vol.6, no.2, pp.1-4, April 2022.

Authors

Haruo KOBAYASHI
  Gunma University

Keyword

circuit and system research,  waveform sampling,  ADC,  DAC,  TDC,  analog IC test