IEICE TRANSACTIONS on Electronics
A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration
Summary :
The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.1
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.6 pp.1026-1034
- Publication Date
- 2012/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.1026
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
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Xiaolei ZHU, Yanfei CHEN, Sanroku TSUKAMOTO, Tadahiro KURODA, "A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 6, pp. 1026-1034, June 2012, doi: 10.1587/transele.E95.C.1026.
Abstract: The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.1
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1026/_p
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@ARTICLE{e95-c_6_1026,
author={Xiaolei ZHU, Yanfei CHEN, Sanroku TSUKAMOTO, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration},
year={2012},
volume={E95-C},
number={6},
pages={1026-1034},
abstract={The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.1
keywords={},
doi={10.1587/transele.E95.C.1026},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration
T2 - IEICE TRANSACTIONS on Electronics
SP - 1026
EP - 1034
AU - Xiaolei ZHU
AU - Yanfei CHEN
AU - Sanroku TSUKAMOTO
AU - Tadahiro KURODA
PY - 2012
DO - 10.1587/transele.E95.C.1026
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2012
AB - The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.1
ER -
English
