This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

This paper describes a high-speed, robust, scalable, and low-cost feed-forward time amplifier that uses phase detectors and variable delay lines. The amplifier works by detecting the time difference between two rising input edges with a phase detector and adjusting the delay of the variable delay line accordingly. A test chip was designed and fabricated in 65 nm CMOS. The measured resulting performance indicates that it is possible to amplify time difference while maintaining high-speed operation.

CMOS amperometric sensors with a microelectrode array offer great potential for counting bacteria because of their low cost, compact size, and ease of use. This paper presents a current-integration-based CMOS amperometric sensor for high-sensitivity bacteria counting. It has a current integrator for noise reduction and reportedly the most large-scale microelectrode array (1024 × 1024). This proposed sensor can count the number of bacteria ranging from a single cell to approximately a million cells. A prototype chip was fabricated using two-poly three-metal (2P3M) 0.6-µm standard CMOS technology. A 7.6 × 7.1-mm2 chip operates from a 5V supply at 1.9mA. In addition, by using the prototype chip, we performed electrochemical measurement and partial 2D imaging of silicone through constant potential amperometry. The measurement results indicate that the proposed sensor chip was able to accurately readout redox current from the 1024 × 1024 sensor array.

In this paper, we present sub-1-V CMOS-based electrophoresis method for small-form-factor biomolecule manipulation that is contained in a microchip. This is the first time this type of device has been presented in the literature. By combining CMOS technology with electroless gold plating, the electrode pitch can be reduced and the required input voltage can be decreased to less than 1 V. We fabricated the CMOS electrophoresis chip in a cost-competitive 0.6 µm standard CMOS process. A sample/hold circuit in each cell is used to generate a constant output from an analog input. After forming gold electrodes using an electroless gold plating technique, we were able to manipulate red food coloring with a 0-0.7 V input voltage range. The results shows that the proposed CMOS chip is effective for electrophoresis-based manipulation.

In this study, a well-shaped microelectrode array (MEA) for fabricating a high-density complementary metal-oxide semiconductor amperometric electrochemical sensor array was designed and verified. By integrating an auxiliary electrode with the well-shaped structure of the MEA, the footprint was reduced and high density and high resolution were also achieved. The results of three-dimensional electrochemical simulations confirmed the effectiveness of the proposed MEA structure and possibility of increasing the density to four times than that achieved by the conventional two-dimensional structure.

A daisy chain of current-driven transmitters in inductive-coupling complementary metal oxide semiconductor (CMOS) links is presented. Transmitter power can be reduced since current is reused by multiple transmitters. Eight transceivers are arranged with a pitch of 20 µm in 0.18 µm CMOS. Transmitter power is reduced by 35% without sacrificing either the data rate (1 Gb/s/ch) or BER (<10-12) by using a 4-transmitter daisy chain. A coding technique for efficient use of daisy chain transmitters is also proposed. With the proposed coding technique, additional power reduction can be achieved.

This brief proposes a solar-cell-assisted wireless biosensing system that operates using a biofuel cell (BFC). To facilitate BFC area reduction for the use of this system in area-constrained continuous glucose monitoring contact lenses, an energy harvester combined with an on-chip solar cell is introduced as a dedicated power source for the transmitter. A dual-oscillator-based supply voltage monitor is employed to convert the BFC output into digital codes. From measurements of the test chip fabricated in 65-nm CMOS technology, the proposed system can achieve 99% BFC area reduction.

This brief presents a slope analog-digital converter (ADC)-based supply voltage monitor (SVM) for biofuel-cell-powered supply-sensing systems operating in a supply voltage range of 0.18-0.35V. The proposed SVM is designed to utilize the output of energy harvester extracting power from biological reactions, realizing energy-autonomous sensor interfaces. A burst pulse generator uses a dynamic leakage suppression logic oscillator to generate a stable clock signal under the sub-threshold region for pulse counting. A slope-based voltage-to-time converter is employed to generate a pulse width proportional to the supply voltage with high linearity. The test chip of the proposed SVM is implemented in 180-nm CMOS technology with an active area of 0.018mm2. It consumes 2.1nW at 0.3V and achieves a conversion time of 117-673ms at 0.18-0.35V with a nonlinearity error of -5.5/+8.3mV, achieving an energy-efficient biosensing frontend.

This work presents an FSK inductive-coupling transceiver using a load-modulated transmitter and LC-oscillator-based receiver for energy-budget-unbalanced applications. By introducing the time-domain load modulated transmitter for FSK instead of the conventional current-driven scheme, energy reduction of the transmitter side is possible. For verifying the proposed scheme, a test chip was fabricated in 65nm CMOS, and two chips were stacked for verifying the inter-chip communication. The measurement results show 0.64fJ/bit transmitter power consumption while its input voltage is 60mV, and the communication distance is 150μm. The footprint of the transmitter is 0.0016mm2.

This work presents the lowest power consumption sub-mm2 supply-modulated OOK transmitter for self-powering a continuous glucose monitoring (CGM) contact lens. By combining the transmitter with a glucose fuel cell that functions as both the power source and a sensing transducer, a self-powered CGM contact lens was developed. The 385×385μm2 test chip implemented in 65-nm standard CMOS technology operates at 270pW with a supply voltage of 0.165V. Self-powered operation of the transmitter using a 2×2mm2 solid-state glucose fuel cell was thus demonstrated.

This paper describes algorithms for generating low intermodulation-distortion (IMD) two-tone sinewaves, for such as communication application ADC testing, using an arbitrary waveform generator (AWG) or a multi-bit ΣΔ DAC inside an SoC. The nonlinearity of the DAC generates distortion components, and we propose here eight methods to precompensate for the IMD using DSP algorithms and produce low-IMD two-tone signals. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of our approach.

This study proposes a design and calibration method for a small-footprint, low-frequency, and low-power gate leakage timer using a differential leakage technique for IoT applications. The proposed gate leakage timer is different from conventional ones because it is composed of two leakage sources and exploits differential leakage current for the charging capacitor. This solution alleviates the inherent trade-off between small-footprint and low-frequency in the conventional gate leakage timer. Furthermore, a calibration method to suppress variations of the output frequency is proposed in this paper. To verify the effectiveness of the proposed gate leakage timer, a test chip was fabricated using 55-nm-DDC-CMOS technology. The test chip successfully demonstrates the highest figure of merit (FoM) of the product of the capacitor area (0.072µm2) and output frequency (0.11Hz), which corresponds to an improvement by a factor of 2,121 compared to the conventional one. It also demonstrates the operation with 4.5pW power consumption. The total footprint can be reduced to be 28µm2, which enables low-cost and low-power IoT edges. The scaling scenario shows that the proposed technique is conducive to technology scaling.

High-resolution bio-imaging is a key component for the advancement of life science. CMOS electronics is one of the promising candidates for emerging high-resolution devices because it offers nano-scale transistors. However, the resolution of the existing CMOS bio-imaging devices is several micrometers, which is insufficient for analyzing small objects such as bacteria and viruses. This paper presents the results of an analysis of the scalability of a current-mode analog-to-time converter (CMATC) to develop a high-resolution CMOS biosensor array. Simulations were performed using 0.6-µm, 0.25-µm, and 0.065-µm CMOS technology nodes. The Simulation results for the power consumption and resolution (cell size) showed that the CMATC has high-scalability and is a promising candidate to enable high-resolution CMOS bio-imaging.