A three-dimensional semiconductor package structure with inter-chip connections was developed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a 10 µm scale fine-wiring pattern and ultra-fine-pitch through vias. This technology features co-existence of the wide-band memory accessibility of a system-on-chip (SoC) and the capability of memory capacity increasing of a system-in-package (SiP) that is made possible by the individual fabrication of memory and logic on independent chips. This technology can improve performance due to memory band widening and a reduction in the power consumed in inter-chip communications. This paper describes the concept, structure, process, and experimental results of prototypes of this package, called SMAFTI (SMAart chip connection with FeedThrough Interposer). This paper also reports the results of the fundamental reliability test of this novel inter-chip connection structure and board-level interconnectivity tests.

A daisy chain of current-driven transmitters in inductive-coupling complementary metal oxide semiconductor (CMOS) links is presented. Transmitter power can be reduced since current is reused by multiple transmitters. Eight transceivers are arranged with a pitch of 20 µm in 0.18 µm CMOS. Transmitter power is reduced by 35% without sacrificing either the data rate (1 Gb/s/ch) or BER (<10-12) by using a 4-transmitter daisy chain. A coding technique for efficient use of daisy chain transmitters is also proposed. With the proposed coding technique, additional power reduction can be achieved.