IEICE TRANSACTIONS on Electronics
A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect
Summary :
A three-dimensional semiconductor package structure with inter-chip connections was developed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a 10 µm scale fine-wiring pattern and ultra-fine-pitch through vias. This technology features co-existence of the wide-band memory accessibility of a system-on-chip (SoC) and the capability of memory capacity increasing of a system-in-package (SiP) that is made possible by the individual fabrication of memory and logic on independent chips. This technology can improve performance due to memory band widening and a reduction in the power consumed in inter-chip communications. This paper describes the concept, structure, process, and experimental results of prototypes of this package, called SMAFTI (SMAart chip connection with FeedThrough Interposer). This paper also reports the results of the fundamental reliability test of this novel inter-chip connection structure and board-level interconnectivity tests.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.12 pp.1512-1522
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1512
- Type of Manuscript
- PAPER
- Category
- Electronic Components
Authors
Yoichiro KURITA
Koji SOEJIMA
Katsumi KIKUCHI
Masatake TAKAHASHI
Masamoto TAGO
Masahiro KOIKE
Koujirou SHIBUYA
Shintaro YAMAMICHI
Masaya KAWANO
Keyword
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Yoichiro KURITA, Koji SOEJIMA, Katsumi KIKUCHI, Masatake TAKAHASHI, Masamoto TAGO, Masahiro KOIKE, Koujirou SHIBUYA, Shintaro YAMAMICHI, Masaya KAWANO, "A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 12, pp. 1512-1522, December 2009, doi: 10.1587/transele.E92.C.1512.
Abstract: A three-dimensional semiconductor package structure with inter-chip connections was developed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a 10 µm scale fine-wiring pattern and ultra-fine-pitch through vias. This technology features co-existence of the wide-band memory accessibility of a system-on-chip (SoC) and the capability of memory capacity increasing of a system-in-package (SiP) that is made possible by the individual fabrication of memory and logic on independent chips. This technology can improve performance due to memory band widening and a reduction in the power consumed in inter-chip communications. This paper describes the concept, structure, process, and experimental results of prototypes of this package, called SMAFTI (SMAart chip connection with FeedThrough Interposer). This paper also reports the results of the fundamental reliability test of this novel inter-chip connection structure and board-level interconnectivity tests.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1512/_p
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@ARTICLE{e92-c_12_1512,
author={Yoichiro KURITA, Koji SOEJIMA, Katsumi KIKUCHI, Masatake TAKAHASHI, Masamoto TAGO, Masahiro KOIKE, Koujirou SHIBUYA, Shintaro YAMAMICHI, Masaya KAWANO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect},
year={2009},
volume={E92-C},
number={12},
pages={1512-1522},
abstract={A three-dimensional semiconductor package structure with inter-chip connections was developed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a 10 µm scale fine-wiring pattern and ultra-fine-pitch through vias. This technology features co-existence of the wide-band memory accessibility of a system-on-chip (SoC) and the capability of memory capacity increasing of a system-in-package (SiP) that is made possible by the individual fabrication of memory and logic on independent chips. This technology can improve performance due to memory band widening and a reduction in the power consumed in inter-chip communications. This paper describes the concept, structure, process, and experimental results of prototypes of this package, called SMAFTI (SMAart chip connection with FeedThrough Interposer). This paper also reports the results of the fundamental reliability test of this novel inter-chip connection structure and board-level interconnectivity tests.},
keywords={},
doi={10.1587/transele.E92.C.1512},
ISSN={1745-1353},
month={December},}
Copy
TY - JOUR
TI - A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect
T2 - IEICE TRANSACTIONS on Electronics
SP - 1512
EP - 1522
AU - Yoichiro KURITA
AU - Koji SOEJIMA
AU - Katsumi KIKUCHI
AU - Masatake TAKAHASHI
AU - Masamoto TAGO
AU - Masahiro KOIKE
AU - Koujirou SHIBUYA
AU - Shintaro YAMAMICHI
AU - Masaya KAWANO
PY - 2009
DO - 10.1587/transele.E92.C.1512
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2009
AB - A three-dimensional semiconductor package structure with inter-chip connections was developed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a 10 µm scale fine-wiring pattern and ultra-fine-pitch through vias. This technology features co-existence of the wide-band memory accessibility of a system-on-chip (SoC) and the capability of memory capacity increasing of a system-in-package (SiP) that is made possible by the individual fabrication of memory and logic on independent chips. This technology can improve performance due to memory band widening and a reduction in the power consumed in inter-chip communications. This paper describes the concept, structure, process, and experimental results of prototypes of this package, called SMAFTI (SMAart chip connection with FeedThrough Interposer). This paper also reports the results of the fundamental reliability test of this novel inter-chip connection structure and board-level interconnectivity tests.
ER -
English
