This paper presents a low-power small-area-overhead physical random number generator utilizing SAR ADC embedded in sensor SoCs. An unpredictable random bit sequence is produced by an existing comparator in typical SAR ADCs, which results in little area overhead. Unlike the other comparator-based physical random number generator, this proposed technique does not require an offset calibration scheme since SAR binary search algorithm automatically converges the two input voltages of the comparator to balance the differential circuit pair. Although the randomness slightly depends on an quantization error due to sharing AD conversion scheme, the input signal distribution enhances the quality of random number bit sequence which can use for various security countermeasures such as masking techniques. Fabricated in 180nm CMOS, 1Mb/s random bit generator achieves high efficiency of 0.72pJ/bit with only 400μm2 area overhead, which occupies less than 0.5% of SAR ADC, while remaining 10-bit AD conversion function.

Reservoir computing (RC) is an attractive alternative to machine learning models owing to its computationally inexpensive training process and simplicity. In this work, we propose EnsembleBloomCA, which utilizes cellular automata (CA) and an ensemble Bloom filter to organize an RC system. In contrast to most existing RC systems, EnsembleBloomCA eliminates all floating-point calculation and integer multiplication. EnsembleBloomCA adopts CA as the reservoir in the RC system because it can be implemented using only binary operations and is thus energy efficient. The rich pattern dynamics created by CA can map the original input into a high-dimensional space and provide more features for the classifier. Utilizing an ensemble Bloom filter as the classifier, the features provided by the reservoir can be effectively memorized. Our experiment revealed that applying the ensemble mechanism to the Bloom filter resulted in a significant reduction in memory cost during the inference phase. In comparison with Bloom WiSARD, one of the state-of-the-art reference work, the EnsembleBloomCA model achieves a 43× reduction in memory cost while maintaining the same accuracy. Our hardware implementation also demonstrated that EnsembleBloomCA achieved over 23× and 8.5× reductions in area and power, respectively.

A daisy chain of current-driven transmitters in inductive-coupling complementary metal oxide semiconductor (CMOS) links is presented. Transmitter power can be reduced since current is reused by multiple transmitters. Eight transceivers are arranged with a pitch of 20 µm in 0.18 µm CMOS. Transmitter power is reduced by 35% without sacrificing either the data rate (1 Gb/s/ch) or BER (<10-12) by using a 4-transmitter daisy chain. A coding technique for efficient use of daisy chain transmitters is also proposed. With the proposed coding technique, additional power reduction can be achieved.

This paper describes an effective model which reproduces the dependence on the source/drain (S/D) process of the reverse short channel effect (RSCE) of the MOSFET threshold voltage (Vth). It is useful for local modeling which is effective within the limited process conditions. The proposed model is based on the physics where the key factor of RSCE is the dopant pile-up in the Si/SiO2 interface. The purpose of the model is for TCAD to be put to actual use as a quick solution tool. The calculation cost is much lower than a pair diffusion model, because the model is implemented in a conventional process simulator that solves one equation for each impurity. The capability of the simplified model is investigated for the dependence of various process conditions on the RSCE. Using our model, we also report the application of both the actual n-channel and p-channel MOSFETs.

Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.

We propose an effective model that can reproduce the reverse short channel effect (RSCE) of the threshold voltage (Vth) of MOSFETs using a conventional process simulator that solves one equation for each impurity. The proposed model is developed for local modeling which is effective within the limited process conditions. The proposed model involves the physics in which RSCE is due to the pile up of channel dopant at the Si/SiO2 interface. We also report the application to actual device design using our model. The calculation cost is much lower than for a pair diffusion model, and device design in an acceptable turn around time is possible.

We propose an effective dopant pile-up model which is useful for device optimization in a short-term. Our purpose is that the model provides speedy calculation for numerous simulations constructed by design of experiment (DoE), and the calibration is also easy in practical range of process condition. The dopant pile-up in the Si/SiO2 interface is calculated using a non-pair diffusion model that solves one equation for each impurity, considering an essential physics where RSCE is due to the dopant pile-up in the Si/SiO2 interface. A non-pair diffusion for dopants and point defects is adequate for time length which can ignore their reactions. The key for the modeling of RSCE is that the dependence on various processes such as channel implantation and annealing conditions can be reproduced in the local process window. The capability of the model is investigated though the comparison to measurements in actual n-channel MOSFETs for different process technologies. We also check the prediction accuracy of the dopant profiles using our model. As a result, the optimization of 4 parameters for 25 jobs based on DoE is possible less than 2 hours using our model.

With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and Vth temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.

In this paper, we propose an effective SOI yield engineering methodology by practical usage of 2D simulations. Process design for systematic yield of Fully-Depleted SOI MOSFET requires specific consideration of floating-body effects and parasitic channel leakage currents. The influence of varied SOI layer thickness to such phenomena is also complicated and substantial. Instead of time-consuming 3D simulators, 2D simulators are used to optimize the process considering these effects in acceptable turn around time. Our methodology is more effective in future scaled-down process with decreased SOI layer thickness.

Substrate noise coupling in RF receiver front-end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65nm CMOS technology. A CMOS digital noise emulator injects high-order harmonic noises in a silicon substrate and induces in-band spurious tones in an RF receiver on the same chip through substrate noise interference. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixed-level simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compared with the measurements. The interference of substrate noise at the 17th harmonics of 124.8MHz — the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1GHz.

A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm2 will be obtained.

Power supply noise waveforms within cryptographic VLSI circuits in a 65nm CMOS technology are captured by using an on-chip voltage waveform monitor (OCM). The waveforms exhibit the correlation of dynamic voltage drops to internal logical activities during Advance Encryption Standard (AES) processing, and causes side-channel information leakage regarding to secret key bytes. Correlation Power Analysis (CPA) is the method of an attack extracting such information leakage from the waveforms. The frequency components of power supply noise contributing the leakage are shown to be localized in an extremely low frequency region. The level of information leakage is strongly associated with the size of increment of dynamic voltage drops against the Hamming distance in the AES processing. The time window of significant importance where the leakage most likely happens is clearly designated within a single clock cycle in the final stage of AES processing. The on-chip power supply noise measurements unveil the facts about side-channel information leakage behind the traditional CPA with on-board sensing of power supply current through a resistor of 1 ohm.

A wireless transceiver utilizing inductive coupling has been proposed for communication between chips in system in a package. This transceiver can achieve high-speed communication by using two-dimensional channel arrays. To increase the total bandwidth in the channel arrays, the density of the transceiver should be improved, which means that the inductor size should be scaled down. This paper discusses the scaling theory based on a constant magnetic field rule. By decreasing the chip thickness with the process scaling of 1/α, the inductor size can be scaled to 1/α and the data rate can be increased by α. As a result, the number of aggregated channels can be increased by α2 and the aggregated data bandwidth can be increased by α3. The scaling theory is verified by simulations and experiments in 350, 250, 180, and 90 nm CMOS.

In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um2 silicon area and consumes 0.18 mW at 1 GS/s.

In this paper, we propose a TCAD driven hot carrier reduction methodology of 3.3 V I/O pMOSFETs design. The hot carrier reliability of surface channel I/O pMOSFET having drain structure in common with core devices has a critical issue. It is substantially important for the high-reliability devices to reduce both drain avalanche and channel hot hole components. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and drive current (ION), SDE/HALO of both core and I/O transistors can be totally optimized for reduction of process-steps and/or photo-masks.