Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit

Sanghoon HWANG; Junho MOON; Minkyu SONG

doi:10.1093/ietele/e91-c.2.213

Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit

Sanghoon HWANG, Junho MOON, Minkyu SONG

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In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an auto-switching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28 mm² in 0.18 µm CMOS technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.2 pp.213-219

Publication Date: 2008/02/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.2.213

Type of Manuscript: PAPER

Category: Electronic Circuits

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Sanghoon HWANG, Junho MOON, Minkyu SONG, "Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 2, pp. 213-219, February 2008, doi: 10.1093/ietele/e91-c.2.213.
Abstract: In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an auto-switching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28 mm² in 0.18 µm CMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.2.213/_p

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@ARTICLE{e91-c_2_213,
author={Sanghoon HWANG, Junho MOON, Minkyu SONG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit},
year={2008},
volume={E91-C},
number={2},
pages={213-219},
abstract={In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an auto-switching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28 mm² in 0.18 µm CMOS technology.},
keywords={},
doi={10.1093/ietele/e91-c.2.213},
ISSN={1745-1353},
month={February},}

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TY - JOUR
TI - Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit
T2 - IEICE TRANSACTIONS on Electronics
SP - 213
EP - 219
AU - Sanghoon HWANG
AU - Junho MOON
AU - Minkyu SONG
PY - 2008
DO - 10.1093/ietele/e91-c.2.213
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2008
AB - In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an auto-switching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28 mm² in 0.18 µm CMOS technology.
ER -