This paper reviews recent world-wide progress in silicon-based photonics-and-optoelectronics in order to provide a context for the papers in this special section of the IEICE Transactions. The impact of present and potential applications is discussed.

LSI on-chip optical interconnections are discussed from the viewpoint of a comparison between optical and electrical interconnections. Based on a practical prediction of our optical device development, optical interconnects will have an advantage over electrical interconnects within a chip that has an interconnect length less than about 10 mm at the hp32-22 nm technology node. Fundamental optical devices and components used in interconnections have also been introduced that are small enough to be placed on top of a Si LSI and that can be fabricated using methods compatible with CMOS processes. A SiON waveguide showed a low propagation loss around 0.3 dB/cm at a wavelength of 850 nm, and excellent branching characteristics were achieved for MMI (multimode interference) branch structures. A Si nano-photodiode showed highly enhanced speed and efficiency with a surface plasmon antenna. By combining our Si nano-photonic devices with the advanced TIA-less optical clock distribution circuits, clock distribution above 10 GHz can be achieved with a small footprint on an LSI chip.

Integration of light sources on a Si chip is one of milestone to establish new paradigm of LSI systems, so-called "silicon photonics." In recent years remarkable progress has been made in the Si wire waveguide technologies for optical interconnection on a Si chip. In this paper, several Er embedded materials based on silicon are surveyed from the standpoint of application to the light emission and amplification devices for silicon photonics. We have concentrated to investigate an erbium silicate (Er₂SiO₅) as a light source medium for silicon photonics. To mention the particular features, this material has a layered structure with 0.86-nm period and a large amount of Er (25at%) as its constituent. The single crystalline nature gives several remarkable properties for the application to silicon photonics. We also discuss our recent studies of Er₂SiO₅ and a possibility of the shorter waveguide amplifier.

Structural defect-free GaPN and InGaPN layers were grown on a Si (100) substrate. Light emitting diodes (LEDs) and Si metal-oxide-semiconductor field effect transistors (MOSFETs), which are elemental devices for optoelectronic integrated circuits(OEICs), were monolithically integrated in a single chip with a Si layer and an InGaPN/GaPN double hetereostructure layer grown on a Si substrate. The developed process flow was based on a conventional MOSFET process flow. It was confirmed that light emission from the LED was modulated by switching the MOSFET. The growth and fabrication process technologies are effective in the realization of monolithic OEICs.

Si-based photonic materials and devices, including SiGe/Si quantum structures, SOI and InGaAs bonded on Si, PL of Si nanocrystals, SOI photonic crystal filter, Si based RCE (Resonant Cavity Enhanced) photodiodes, SOI TO (thermai-optical) switch matrix were investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main results in recent years are presented in the paper. The mechanism of PL from Si NCs embedded in SiO₂ matrix was studied, a greater contribution of the interface state recombination (PL peak in 850~900 nm) is associated with larger Si NCs and higher interface state density. Ge dots with density of order of 10¹¹ cm^-2 were obtained by UHV/CVD growth and 193 nm excimer laser annealing. SOI photonic crystal filter with resonant wavelength of 1598 nm and Q factor of 1140 was designed and made. Si based hybrid InGaAs RCE PD with η of 34.4% and FWHM of 27 nm were achieved by MOCVD growth and bonding technology between InGaAs epitaxial and Si wafers. A 1616 SOI optical switch matrix were designed and made. A new current driving circuit was used to improve the response speed of a 44 SOI rearrangeable nonblocking TO switch matrix, rising and falling time is 970 and 750 ns, respectively.

In this review paper we showcase recent activities on silicon photonics science and technology research in Hong Kong regarding two important topical areas--microresonator devices and optical nonlinearities. Our work on silicon microresonator filters, switches and modulators have shown promise for the nascent development of on-chip optoelectronic signal processing systems, while our studies on optical nonlinearities have contributed to basic understanding of silicon-based optically-pumped light sources and helium-implanted detectors. Here, we review our various passive and electro-optic active microresonator devices including (i) cascaded microring resonator cross-connect filters, (ii) NRZ-to-PRZ data format converters using a microring resonator notch filter, (iii) GHz-speed carrier-injection-based microring resonator modulators and 0.5-GHz-speed carrier-injection-based microdisk resonator modulators, and (iv) electrically reconfigurable microring resonator add-drop filters and electro-optic logic switches using interferometric resonance control. On the nonlinear waveguide front, we review the main nonlinear optical effects in silicon, and show that even at fairly modest average powers two-photon absorption and the accompanied free-carrier linear absorption could lead to optical limiting and a dramatic reduction in the effective lengths of nonlinear devices.

We propose and demonstrate a simple one-bus two-ring configuration where the two rings are mutually coupled that has advantages over the one-ring structure. Unlike a one cavity system, it can exhibit near critically-coupled transmission with a broader range of loss. It can also significantly enhance the cavity finesse by simply making the second ring twice the size of the bus-coupled one, with the enhancement proportional to the intensity buildup in the second ring.

The historical review of Taiwan's researching activities on the features of PECVD grown SiO_x are also included to realize the performance of Si nanocrystal based MOSLED made by such a Si-rich SiO_x film with embedded Si nanocrystals on conventional Si substrate. A surface nano-roughened Si substrate with interfacial Si nano-pyramids at SiO_x/Si interface are also reviewed, which provide the capabilities of enhancing the surface roughness induced total-internal-reflection relaxation and the Fowler-Nordheim tunneling based carrier injection. These structures enable the light emission and extraction from a metal-SiO_x-Si MOSLED.

Effect of the post-growth annealing on the morphology of a Ge mesa selectively grown on Si was studied from the viewpoint of near-infrared photodiode applications. By ultrahigh-vacuum chemical vapor deposition, Ge mesas were selectively grown at 600 on Si (001) substrates partially covered with SiO₂ masks. The as-grown Ge mesas showed trapezoidal cross-sections having a top (001) surface and {311} sidewall facets, as similar to previous reports. However, after the subsequent post-growth annealing at ~800 in the ultrahigh-vacuum chamber, the mesas were deformed into rounded shapes having a depression at the center and mounds near the edges. Such a deformation cannot be observed for the samples annealed once after cooled and exposed to the air. The residual hydrogen atoms on the Ge surface from the germane (GeH₄) decomposition is regarded as a trigger to the observed morphological instability, while the final mesa shape is determined in order to minimize a sum of the surface and/or strain energies.

This paper is aimed to present the design and feasibility investigations of adopting the available on-site optical inspection system, which is commonly used for steel plate dimension measurement, to supply on-line dynamic gap measurements of a non-contacting conveyance structure in a steel mill. Adequate software and hardware implementations based on digital image processing techniques have been adapted to the entire system formulations and estimations. Results show that the system can supply accurate and rapid gap measurements and thus can fulfill the design and operational objectives.

This work presents a technique to enhance the performance of the conventional PMOS Colpitts VCO circuit. This technique is accomplished by adding an NMOS cross-coupled pair under the traditional differential Colpitts VCO to enhance the oscillator startup condition and its efficiency. The analytics also support this viewpoint and present a device- choosing method to optimize the output power and phase noise. This new VCO can also be applied to realize the QVCO circuit, because the coupling transistors can be placed in parallel, connecting with the transistors in the NMOS cross-coupled pair, to achieve the proper coupling between individual VCOs. To verify the proposed design concept, two prototypes, which are VCO and QVCO operated at 2.4 GHz and fabricated in CMOS 0.25-µm technology, are designed and tested. The measurement results show that the performance of VCO demonstrates a FOM of about 180 dBC/Hz, and the phase noise of QVCO is -116 dBc/Hz at the 1 MHz offset from oscillation frequency.

A wireless transceiver utilizing inductive coupling has been proposed for communication between chips in system in a package. This transceiver can achieve high-speed communication by using two-dimensional channel arrays. To increase the total bandwidth in the channel arrays, the density of the transceiver should be improved, which means that the inductor size should be scaled down. This paper discusses the scaling theory based on a constant magnetic field rule. By decreasing the chip thickness with the process scaling of 1/α, the inductor size can be scaled to 1/α and the data rate can be increased by α. As a result, the number of aggregated channels can be increased by α² and the aggregated data bandwidth can be increased by α³. The scaling theory is verified by simulations and experiments in 350, 250, 180, and 90 nm CMOS.

This work describes a 12 b 200 kS/s 0.52 mA 0.47 mm² ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200 kS/s and 10 kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18 µm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55 dB and 70 dB at all sampling frequencies up to 200 kS/s, respectively. The ADC occupies an active die area of 0.47 mm² and consumes 0.94 mW at 200 kS/s and 0.63 mW at 10 kS/s with a 1.8 V supply.

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an auto-switching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28 mm² in 0.18 µm CMOS technology.

The wave absorber composed of cylindrical bars arranged periodically and metallic mesh for improving visibility is proposed for ETC, and characteristics of reflectivity and shielding effect are evaluated analytically and experimentally. As a result, reflectivity of -10 dB and shielding effect of -25 dB are obtained for circularly polarized wave when the gap between cylindrical bars is 30 mm. Therefore, realization of proposed wave absorber for installing between ETC lanes can be clarified.

A novel dual mode bandpass filter (BPF) with improved spurious response is presented in this letter. To obtain low insertion loss, the coupling structure using the dual mode resonator and the feeding scheme using coplanar-waveguide (CPW) are constructed on the two sides of a dielectric substrate. A defected ground structure (DGS) is designed on the ground plane of the CPW to achieve the goal of spurious suppression of the filter. The filter has been investigated numerically and experimentally. Measured results show a good agreement with the simulated analysis.

A power-efficient Dickson-based charge pump circuit is proposed and verified in this paper. Using a PMOS transfer switch in the new circuit solves the problem of the output voltage loss and its body control switch can suppress the parasitic bipolar action. Comparing this new one with the conventional circuit, the new circuit generates output voltage as high as 2.9 V_DD while the conventional one only 2 V_DD. For their efficiency values, the new circuit has better efficiency than the conventional one by as much as 14.5% with the area overhead of 12.2% using 3.5-µm and 40-V CMOS high-voltage process.

A current-mode squarer/divider circuit with a novel translinear cell is presented for automotive applications. The proposed circuit technique increases the accuracy of the squarer/divider function with better input dynamic range and temperature insensitivity. Simulation results show that the variation of the output current is within ±0.2% over the temperature range from -40 to 140.

For real time image processing, a readout circuit for an infrared focal plane array (IRFPA) involving a new edge detection technique has been proposed in this letter. A non-uniformity correction unit (NUC), essential in an IRFPA because of bad non-uniformity characteristics of IR sensors is eliminated in this circuit by using a noise tolerant edge detection technique. In addition, real time edge detection can be possible, because of pixel-level integration and parallel processing. The proposed readout circuit shows an approximately three to nine times better edge error rate than other available methods using pixel-level parallel processing.

This paper describes novel CMOS level-conversion flip-flops for use in low-power SoCs with clustered voltage scaling. These flip-flops feed outputs directly into the front stage to support self-resetting and conditional operations. They thus have simple structures to avoid clock level shifting and redundant transitions, leading to substantial improvements in terms of power and area. The comparison results indicate that the proposed level-conversion flip-flops achieve power and area savings up to 50% and 31%, respectively, with no speed degradation as compared to conventional level-conversion flip-flops.

This paper proposes a new reset driving waveform to widen the driving margin under a low address voltage in AC-PDPs. The proposed reset waveform alters the wall charge distribution between the X-Y electrodes by applying an X-ramp bias prior to an address-period, thereby lowering the minimum level of the scan pulse (ΔV_y) during an address-period without any misfiring discharge in the off-cells. When adopting the proposed reset waveform, the address discharge time delay is reduced by about 200 ns at an address voltage of 35 V, while the related dynamic driving margin is wide under a low address voltage condition. The related phenomena are also examined using the V_t close-curve method.