This work describes an 8b 240 MS/s CMOS ADC as one of embedded core circuits for high-performance displays based on low-noise on-chip references and dual-mode inputs with the requirements of limited pins, low power, and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipeline architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip current and voltage references to improve noise performance with a power-off function for portable applications. The prototype ADC is implemented in a 0.18 µm CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The prototype ADC shows the measured DNL and INL within 0.49LSB and 0.69LSB, and the SNDR and SFDR exceeding 38 dB and 50 dB for inputs up to the Nyquist frequency at 240 MS/s. The ADC consumes 104 mW at 240 MS/s and an active die area is 1.36 mm2 .

This work describes a 12 b 200 kS/s 0.52 mA 0.47 mm2 ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200 kS/s and 10 kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18 µm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55 dB and 70 dB at all sampling frequencies up to 200 kS/s, respectively. The ADC occupies an active die area of 0.47 mm2 and consumes 0.94 mW at 200 kS/s and 0.63 mW at 10 kS/s with a 1.8 V supply.