We present an improvement to the existing steganography-based bandwidth extension scheme. Enhanced WB (wideband) speech quality is achieved by embedding multiple highband spectral gains into a G.711 bitstream. The number of spectral gains is selected by optimizing the quantity of the embedding data with respect to the quality of the extended WB speech. Compared to the existing method, the proposed scheme improves the WB PESQ (Perceptual Evaluation of Speech Quality) score by 0.334 with negligible degradation of the embedded narrowband speech.

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core circuits for high-performance displays based on low-noise on-chip references and dual-mode inputs with the requirements of limited pins, low power, and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipeline architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip current and voltage references to improve noise performance with a power-off function for portable applications. The prototype ADC is implemented in a 0.18 µm CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The prototype ADC shows the measured DNL and INL within 0.49LSB and 0.69LSB, and the SNDR and SFDR exceeding 38 dB and 50 dB for inputs up to the Nyquist frequency at 240 MS/s. The ADC consumes 104 mW at 240 MS/s and an active die area is 1.36 mm2 .

This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.

In numerical simulations of microwave structures using the alternating-direction implicit finite-difference time-domain (ADI-FDTD) method, the time marching scheme comprises two sub-iterations, where different updating schemes for evaluating E and H fields at each sub-iteration can be adopted. In this paper, the E-field implicit-updating (EFIU) and H-field implicit-updating (HFIU) schemes are compared with each other especially with regard to the implementation of local boundary conditions.