IEICE TRANSACTIONS on Electronics
A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems
Summary :
This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.9 pp.1194-1200
- Publication Date
- 2009/09/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1194
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Young-Ju KIM, Kyung-Hoon LEE, Myung-Hwan LEE, Seung-Hoon LEE, "A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 9, pp. 1194-1200, September 2009, doi: 10.1587/transele.E92.C.1194.
Abstract: This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1194/_p
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@ARTICLE{e92-c_9_1194,
author={Young-Ju KIM, Kyung-Hoon LEE, Myung-Hwan LEE, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems},
year={2009},
volume={E92-C},
number={9},
pages={1194-1200},
abstract={This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.},
keywords={},
doi={10.1587/transele.E92.C.1194},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1194
EP - 1200
AU - Young-Ju KIM
AU - Kyung-Hoon LEE
AU - Myung-Hwan LEE
AU - Seung-Hoon LEE
PY - 2009
DO - 10.1587/transele.E92.C.1194
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2009
AB - This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.
ER -
English
