This new design uses a low power embedded controller (EC) in cooperation with the BIOS of a notebook (NB) computer, both to accomplish dynamic adjustment and to maintain a required performance level of the battery mode of the notebook. In order to extend the operation time at the battery mode, in general, the notebook computer will directly reduce the clock rate and then reduce the performance. This design can obtain the necessary balance of the performance and the power consumption by using both the EC and the BIOS cooperatively to implement the dynamic control of both the CPU and the GPU frequency to maintain the system performance at a sufficient level for a high speed and high resolution video game. In contrast, in order to maintain a certain notebook performance, in terms of battery life it will be necessary to make some trade-offs.

With the development of spaceborne synthetic aperture radar (SAR), ultra-high spatial resolution has become a hot topic in recent years. The system with high spatial resolution requests large range bandwidths and long azimuth integration time. However, due to the long azimuth integration time, many problems arise, which cannot be ignored in the operational ultra-high resolution spotlight mode. This paper investigates two critical issues that need to be noticed for the full-aperture processing of ultra-high resolution spaceborne SAR spotlight data. The first one is the inaccuracy of the traditional hyperbolic range model (HRM) when the system approaches decimeter range resolution. The second one is the azimuth spectral folding phenomenon. The problems mentioned above result in significant degradation of the focusing effect. Thus, to solve these problems, a full-aperture processing scheme is proposed in this paper which combines the superiorities of two generally utilized processing algorithms: the precision of one-step motion compensation (MOCO) algorithm and the efficiency of modified two-step processing approach (TSA). Firstly, one-step MOCO algorithm, a state-of-the-art MOCO algorithm which has been applied in ultra-high resolution airborne SAR systems, can precisely correct for the error caused by spaceborne curved orbit. Secondly, the modified TSA can avoid the phenomenon of azimuth spectrum folding effectively. The key point of the modified TSA is the deramping approach which is carried out via the convolution operation. The reference function, varying with the instantaneous range frequency, is adopted by the convolution operation for obtaining the unfolding spectrum in azimuth direction. After these operations, the traditional wavenumber domain algorithm is available because the error caused by spaceborne curved orbit and the influence of the spectrum folding in azimuth direction have been totally resolved. Based on this processing scheme, the ultra-high resolution spaceborne SAR spotlight data can be well focused. The performance of the full-aperture processing scheme is demonstrated by point targets simulation.

Conventional target recognition methods usually suffer from information-loss and target-aspect sensitivity when applied to radar high resolution range profile (HRRP) recognition. Thus, Effective establishment of robust and discriminatory feature representation has a significant performance improvement of practical radar applications. In this work, we present a novel feature extraction method, based on modified collaborative auto-encoder, for millimeter-wave radar HRRP recognition. The latent frame-specific weight vector is trained for samples in a frame, which contributes to retaining local information for different targets. Experimental results demonstrate that the proposed algorithm obtains higher target recognition accuracy than conventional target recognition algorithms.

This paper presents a study of the applicability of clusters of GPUs to high-resolution 3D simulations of cardiac electrophysiology. By experimenting with representative cardiac cell models and ODE solvers, in association with solving the monodomain equation, we quantitatively analyze the obtainable computational capacity of GPU clusters. It is found that for a 501×501×101 3D mesh, which entails a 0.1mm spatial resolution, a 128-GPU cluster only needs a few minutes to carry out a 100,000-time-step cardiac excitation simulation that involves a four-variable cell model. Even higher spatial and temporal resolutions are achievable for such simplified mathematical models. On the other hand, our experiments also show that a dramatically larger cluster of GPUs is needed to handle a very detailed cardiac cell model.

Battery life and outdoor visibility are two of the most important features for mobile applications today. It is desirable to achieve both low power consumption and excellent outdoor visibility on the display device at the same time. We have previously reported a new RGBW method to realize low power consumption and high luminance with high image quality. In this paper, the basic concept of a new RGBW calculation utilizing an “Extended HSV color space” model is described, and also its performance, such as low power consumption, color image reproducibility and outdoor visibility is presented. The new method focuses on the luminance-increase ratio by means of a White signal for the display image data, and derives the appropriate RGBW signal and backlight PWM signal for every frame period. This dynamically controlled system solves the problems of conventional RGBW systems, and realizes the same image quality as a corresponding RGB display. In order to quantify its color image reproducibility, a spectroscopic measurement has been completed using the Macbeth Color Chart. In addition, the advantages of high luminance by the new RGBW method is described. The converted tone curve with an RGBW method provides very high luminance, such as 1,000cd/m2, and improved outdoor visibility. Finally, a newly developed 4.38-inch full-HD (1,080 × 1,920) 503ppi prototype LCD utilizing this new RGBW technology is described.

In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 38402160@60 fps decoding at less than 133 MHz, with 37.2 k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 44 block to DRAM.

This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.

In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD@60 fps sequences at less than 100 MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 2464 two-port SRAM as internal buffer is required in this design. When synthesized with SMIC 130 nm process, the architecture costs a gate count of 30.2 k, which is competitive considering its high performance.

This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.

We propose a flexible video CODEC system for super-high-resolution videos such as those utilizing 4k2k pixel. It uses the spatially parallel encoding approach and has sufficient scalability for the target video resolution to be encoded. A video shift and padding function has been introduced to prevent the image quality from being degraded when different active line systems are connected. The switchable cascade multiplexing function of our system enables various super-high-resolutions to be encoded and super-high-resolution video streams to be recorded and played back using a conventional PC. A two-stage encoding method using the complexity of each divided image has been introduced to equalize encoding quality among multiple divided videos. System Time Clock (STC) sharing has also been implemented in this CODEC system to absorb the disparity in the times streams are received between channels. These functions enable highly-efficient, high-quality encoding for super-high-resolution video.

Target shape estimation with UWB pulse radars is a promising imaging technique for household robots. We have already proposed a fast imaging algorithm, SEABED, that is based on a reversible transform BST (Boundary Scattering Transform) between the received signals and the target shape. However, the target image obtained by SEABED deteriorates in a noisy environment because it utilizes a derivative of received data. In this paper, we propose a robust imaging method with an envelope of circles. We clarify by numerical simulation that the proposed method can realize a level of robust and fast imaging that cannot be achieved by the original SEABED.

UWB pulse radars enable us to measure a target location with high range-resolution, and so are applicable for measurement systems for robots and automobile. We have already proposed a robust and fast imaging algorithm with an envelope of circles, which is suitable for these applications. In this method, we determine time delays from received signals with the matched filter for a transmitted waveform. However, scattered waveforms are different from transmitted one depending on the target shape. Therefore, the resolution of the target edges deteriorates due to these waveform distortions. In this paper, a high-resolution imaging algorithm for convex targets is proposed by iteration of the shape and waveform estimation. We show application examples with numerical simulations and experiments, and confirm its capability to detect edges of an object.

A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.

We present the 10-bit current driver LSI with 2-set current digital-to-analog converters (DACs) and output channel current sample and hold (S/H) circuits for large-size and high-resolution active matrix organic light emitting diode (AMOLED) display applications. This current driver LSI has 300 output channels and the output current ranges from 0 µA to 290 µA. The maximum output current level can be controlled by 2-bit control signals because the maximum output current level depends on display size and resolution. The chip was fabricated using 0.65µm BiCMOS process and characterized. The chip size is 16.8 mm3.6 mm. Experimental results show that the output current DNL is less than 0.4 LSB and that INL is less than 1.5 LSB. This is good enough to apply 15.5 inch WXGA (1280RGB768) AMOLED displays.

We have introduced an extremely high resolution video system 'Super Hi-Vision' at the Kyushu National Museum. This feature opened in October 2005 with the purpose of exhibiting high-quality images of national treasures and traditional arts and crafts to its visitors. The system achieves high resolution using the spatial pixel offset method, quadrupling the horizontal and vertical resolution of HDTV. To display the images with high fidelity, it is important to manipulate the images on the basis of the system characteristics. This paper reports on the efforts to ensure image quality for this Super Hi-Vision System, focusing on resolution and color reproduction.

The objective of this study was to explore suitable spatial filters for inverse estimation of cortical potentials from the scalp electroencephalogram. The effect of incorporating noise covariance into inverse procedures was examined by computer simulations. The parametric projection filter, which allows inverse estimation with the presence of information on the noise covariance, was applied to an inhomogeneous three-concentric-sphere model under various noise conditions in order to estimate the cortical potentials from the scalp potentials. The present simulation results suggest that incorporation of information on the noise covariance allows better estimation of cortical potentials, than inverse solutions without knowledge about the noise covariance, when the correlation between the signal and noise is low. The method for determining the optimum regularization parameter, which can be applied for parametric inverse techniques, is also discussed.

The high-resolution frequency estimators most commonly used, such as Least Square (LS) method based on AR model, MVSE, MUSIC and ESPRIT, determine estimates of the sinusoidal frequencies from the sample noise-corrupted data. In this paper, a new frequency estimation method named Pole-Placement Least Square (PPLS) is presented, which is a modified LS method with a certain number of model poles restricted to the unit circle. The statistical performance of PPLS is studied numerically, and compared with the Cramer-Rao bound as well as the statistical performance corresponding to the LS methods. PPLS is shown to have higher resolution than the conventional LS method. The relationship between poles location and its resolution is also discussed in detail.

The purpose of our study is to estimate the imaging of ischemic myocardial muscles in rats. The magnetocardiograms (MCG) of rats were measured by a 12-channel high resolution gradiometer, which consisted of 5 mm diameter pick-up coils with a 7.5 mm distance between each coil. MCGs of seven male rats were measured in a magnetically shielded room pre and post coronary artery occlusion. The source imaging was estimated by minimum norm estimation (MNE). Changes of the current source imaging pre- and post coronary artery occlusion were clarified. As a result, in the ST segment, the current distribution significantly increased at the ischemic area. In the T wave, the direction of the current distribution clearly shifted to the left thorax. We proved that the increased area of the current distribution in the ST segment was related to the ischemic area of the ventricular muscles.

We proposed a new method to evaluate display legibility as a function of resolution. This method was able to evaluated display legibility without being restricted to the display resolution. Using this method, subjective psychological experiments were carried out to investigate display resolution, which provides legibility, in observing small characters. Samples viewed by subjects were images displayed on a high-resolution TFT-LCD that we developed, CRT images and printed documents for comparison. We have found that TFT-LCD legibility was much better than that of CRT, and that minimum resolution of about 175 dpi was needed for use in legible document viewers.

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.